MT29F2G08ABAEAH4-IT:E Micron Technology Inc, MT29F2G08ABAEAH4-IT:E Datasheet - Page 52

• Manufacturer Part Number: MT29F2G08ABAEAH4-IT:E
• Description: IC FLASH 2G 3.3V SLC 63VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT29F2G08ABAEAH4-IT:E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Cell Type: NAND
• Density: 2Gb
• Interface Type: Parallel
• Address Bus: 28b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / Rohs Status: Compliant

RANDOM DATA INPUT (85h)
Figure 34: RANDOM DATA INPUT (85h) Operation
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
Cycle type
I/O[7:0]
RDY
As defined for PAGE
(CACHE) PROGRAM
D
The RANDOM DATA INPUT (85h) command changes the column address of the selec-
ted cache register and enables data input on the last-selected die (LUN). This command
is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also
accepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles contain-
ing the column address, puts the selected die (LUN) into data input mode. After the
second address cycle is issued, the host must wait at least
The selected die (LUN) stays in data input mode until another valid command is issued.
Though data input mode is enabled, data input from the host is optional. Data input
begins at the column address specified.
The RANDOM DATA INPUT (85h) command is allowed after the required address cy-
cles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following
commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
CACHE (80h-15h), PROGRAM FOR INTERNAL DATA MOVE (85h-10h), and PROGRAM
FOR TWO-PLANE INTERNAL DATA MOVE (85h-11h).
In devices that have more than one die (LUN) per target, the RANDOM DATA INPUT
(85h) command can be used with other commands that support interleaved die (multi-
LUN) operations.
Dn
IN
Dn + 1
D
IN
Command
85h
Address
C1
52
Address
C2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x8, x16 NAND Flash Memory
t
ADL
Column Address Operations
D
Dk
IN
As defined for PAGE
(CACHE) PROGRAM
t
Dk + 1
ADL before inputting data.
D
IN
© 2009 Micron Technology, Inc. All rights reserved.
Dk + 2
D
IN