MT29F2G08ABAEAH4-IT:E Micron Technology Inc, MT29F2G08ABAEAH4-IT:E Datasheet - Page 59

• Manufacturer Part Number: MT29F2G08ABAEAH4-IT:E
• Description: IC FLASH 2G 3.3V SLC 63VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT29F2G08ABAEAH4-IT:E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Cell Type: NAND
• Density: 2Gb
• Interface Type: Parallel
• Address Bus: 28b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / Rohs Status: Compliant

Figure 38: READ PAGE CACHE SEQUENTIAL (31h) Operation
READ PAGE CACHE RANDOM (00h-31h)
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
Cycle type
I/O[7:0]
RDY
Command
00h
Page Address M
Address x5
The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and
page into the data register while the previous page is output from the cache register.
This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is
also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
To issue this command, write 00h to the command register, then write n address cycles
to the address register, and conclude by writing 31h to the command register. The col-
umn address in the address specified is ignored. The die (LUN) address must match the
same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applica-
ble, the previous READ PAGE CACHE RANDOM (00h-31h) command.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for
busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is
available and that the specified page is copying from the NAND Flash array to the data
register. At this point, data can be output from the cache register beginning at column
address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the
column address of the data being output from the cache register.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command
followed by the READ MODE (00h) command must be used to select only one die
(LUN) and prevent bus contention.
Command
30h
t WB
t R
RR
Command
31h
t WB
t
RCBSY. After
t RCBSY
59
t RR
t
RCBSY, R/B# goes HIGH and the die (LUN) is
D
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D0
OUT
2Gb: x8, x16 NAND Flash Memory
Page M
D
…
OUT
D
Dn
OUT
Command
© 2009 Micron Technology, Inc. All rights reserved.
31h
t WB
Read Operations
t RCBSY
t RR
Page M+1
D
D0
OUT