MT29F2G08ABAEAH4-IT:E Micron Technology Inc, MT29F2G08ABAEAH4-IT:E Datasheet - Page 6

• Manufacturer Part Number: MT29F2G08ABAEAH4-IT:E
• Description: IC FLASH 2G 3.3V SLC 63VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT29F2G08ABAEAH4-IT:E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Cell Type: NAND
• Density: 2Gb
• Interface Type: Parallel
• Address Bus: 28b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / Rohs Status: Compliant

List of Figures
Figure 1: Marketing Part Number Chart ........................................................................................................... 2
Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ............................................................................................... 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ....................................................................................... 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL .............................................................................................................. 12
Figure 6: 63-Ball VFBGA (10.5mm x 13mm) .................................................................................................... 13
Figure 7: 63-Ball VFBGA (9mm x 11mm) ......................................................................................................... 14
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ........................................................................... 15
Figure 9: Array Organization – MT29F2G08 (x8) .............................................................................................. 16
Figure 10: Array Organization – MT29F2G16 (x16) .......................................................................................... 17
Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 19
Figure 12: Asynchronous Address Latch Cycle ................................................................................................ 20
Figure 13: Asynchronous Data Input Cycles ................................................................................................... 21
Figure 14: Asynchronous Data Output Cycles ................................................................................................. 22
Figure 15: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 23
Figure 16: READ/BUSY# Open Drain ............................................................................................................. 24
Figure 17:
Figure 18:
Figure 19: I
Figure 20: I
Figure 21: TC vs. Rp ....................................................................................................................................... 27
Figure 22: R/B# Power-On Behavior ............................................................................................................... 28
Figure 23: RESET (FFh) Operation ................................................................................................................. 32
Figure 24: READ ID (90h) with 00h Address Operation .................................................................................... 33
Figure 25: READ ID (90h) with 20h Address Operation .................................................................................... 33
Figure 26: READ PARAMETER (ECh) Operation .............................................................................................. 36
Figure 27: READ UNIQUE ID (EDh) Operation ............................................................................................... 41
Figure 28: SET FEATURES (EFh) Operation .................................................................................................... 43
Figure 29: GET FEATURES (EEh) Operation ................................................................................................... 44
Figure 30: READ STATUS (70h) Operation ...................................................................................................... 48
Figure 31: READ STATUS ENHANCED (78h) Operation .................................................................................. 49
Figure 32: RANDOM DATA READ (05h-E0h) Operation .................................................................................. 50
Figure 33: RANDOM DATA READ TWO-PLANE (06h-E0h) Operation .............................................................. 51
Figure 34: RANDOM DATA INPUT (85h) Operation ........................................................................................ 52
Figure 35: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 54
Figure 36: READ PAGE (00h-30h) Operation ................................................................................................... 58
Figure 37: READ PAGE (00h-30h) Operation with Internal ECC Enabled .......................................................... 58
Figure 38: READ PAGE CACHE SEQUENTIAL (31h) Operation ........................................................................ 59
Figure 39: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 60
Figure 40: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 61
Figure 41: READ PAGE TWO-PLANE (00h-00h-30h) Operation ....................................................................... 63
Figure 42: PROGRAM PAGE (80h-10h) Operation ........................................................................................... 65
Figure 43: PROGRAM PAGE CACHE (80h–15h) Operation (Start) .................................................................... 67
Figure 44: PROGRAM PAGE CACHE (80h–15h) Operation (End) ..................................................................... 67
Figure 45: PROGRAM PAGE TWO-PLANE (80h–11h) Operation ...................................................................... 69
Figure 46: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 70
Figure 47: ERASE BLOCK TWO-PLANE (60h–D1h) Operation ......................................................................... 71
Figure 48: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ............................................................... 73
Figure 49: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ................... 73
Figure 50: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 74
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
t
t
Fall and
Fall and
OL
OL
vs. Rp (V
vs. Rp (1.8V V
t
t
Rise (3.3V V
Rise (1.8V V
CC
= 3.3V V
CC
) ....................................................................................................................... 26
CC
CC
CC
) ................................................................................................................ 25
) ................................................................................................................ 25
) .............................................................................................................. 26
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2Gb: x8, x16 NAND Flash Memory
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