MT29F2G08ABAEAH4-IT:E Micron Technology Inc, MT29F2G08ABAEAH4-IT:E Datasheet - Page 7

• Manufacturer Part Number: MT29F2G08ABAEAH4-IT:E
• Description: IC FLASH 2G 3.3V SLC 63VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT29F2G08ABAEAH4-IT:E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Cell Type: NAND
• Density: 2Gb
• Interface Type: Parallel
• Address Bus: 28b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / Rohs Status: Compliant

Micron Confidential and Proprietary
2Gb: x8, x16 NAND Flash Memory
Features
Figure 51: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ........... 74
Figure 52: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ....................................................... 74
Figure 53: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................. 75
Figure 54: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation ................................... 75
Figure 55: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 77
Figure 56: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 77
Figure 57: UNLOCK Operation ...................................................................................................................... 78
Figure 58: LOCK Operation ............................................................................................................................ 79
Figure 59: LOCK TIGHT Operation ................................................................................................................ 80
Figure 60: PROGRAM/ERASE Issued to Locked Block ..................................................................................... 81
Figure 61: BLOCK LOCK READ STATUS ......................................................................................................... 81
Figure 62: BLOCK LOCK Flowchart ................................................................................................................ 82
Figure 63: OTP DATA PROGRAM (After Entering OTP Operation Mode) .......................................................... 85
Figure 64: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation
Mode) ........................................................................................................................................................ 86
Figure 65: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................ 87
Figure 66: OTP DATA READ .......................................................................................................................... 88
Figure 67: OTP DATA READ with RANDOM DATA READ Operation ................................................................ 89
Figure 68: TWO-PLANE PAGE READ .............................................................................................................. 91
Figure 69: TWO-PLANE PAGE READ with RANDOM DATA READ ................................................................... 92
Figure 70: TWO-PLANE PROGRAM PAGE ...................................................................................................... 92
Figure 71: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT .......................................................... 93
Figure 72: TWO-PLANE PROGRAM PAGE CACHE MODE ............................................................................... 94
Figure 73: TWO-PLANE INTERNAL DATA MOVE ........................................................................................... 95
Figure 74: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ............................ 96
Figure 75: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT ............................................... 97
Figure 76: TWO-PLANE BLOCK ERASE .......................................................................................................... 98
Figure 77: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ........................................................................ 98
Figure 78: Spare Area Mapping (x8) ............................................................................................................... 102
Figure 79: Spare Area Mapping (x16) ............................................................................................................. 103
Figure 80: RESET Operation ......................................................................................................................... 112
Figure 81: READ STATUS Cycle ..................................................................................................................... 112
Figure 82: READ STATUS ENHANCED Cycle ................................................................................................. 113
Figure 83: READ PARAMETER PAGE ............................................................................................................. 113
Figure 84: READ PAGE ................................................................................................................................. 114
Figure 85: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 115
Figure 86: RANDOM DATA READ ................................................................................................................. 116
Figure 87: READ PAGE CACHE SEQUENTIAL ................................................................................................ 117
Figure 88: READ PAGE CACHE RANDOM ..................................................................................................... 118
Figure 89: READ ID Operation ...................................................................................................................... 119
Figure 90: PROGRAM PAGE Operation .......................................................................................................... 119
Figure 91: PROGRAM PAGE Operation with CE# “Don’t Care” ....................................................................... 120
Figure 92: PROGRAM PAGE Operation with RANDOM DATA INPUT ............................................................. 120
Figure 93: PROGRAM PAGE CACHE .............................................................................................................. 121
Figure 94: PROGRAM PAGE CACHE Ending on 15h ....................................................................................... 121
Figure 95: INTERNAL DATA MOVE ............................................................................................................... 122
Figure 96: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ...................................................... 122
Figure 97: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled ................ 123
Figure 98: ERASE BLOCK Operation .............................................................................................................. 123
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m69a_2gb_nand.pdf – Rev. H 09/10 EN
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