MT29F2G08ABAEAH4-IT:E Micron Technology Inc, MT29F2G08ABAEAH4-IT:E Datasheet - Page 90

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MT29F2G08ABAEAH4-IT:E

Manufacturer Part Number
MT29F2G08ABAEAH4-IT:E
Description
IC FLASH 2G 3.3V SLC 63VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F2G08ABAEAH4-IT:E

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
2G (256M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
63-VFBGA
Cell Type
NAND
Density
2Gb
Interface Type
Parallel
Address Bus
28b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
VFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
256M
Supply Current
35mA
Mounting
Surface Mount
Pin Count
63
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / Rohs Status
Compliant

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Two-Plane Operations
Two-Plane Addressing
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. The
planes are addressed via the low-order block address bits. Specific details are provided
in Device and Array Organization.
Two-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Two-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing two-plane program or erase operations, use the READ STATUS (70h) com-
mand and check whether the previous operation(s) failed. If the READ STATUS (70h)
command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the READ
STATUS ENHANCED (78h) command to determine which plane operation failed.
Two-plane commands require multiple, five-cycle addresses, one address per operation-
al plane. For a given two-plane operation, these addresses are subject to the following
requirements:
• The LUN address bit(s) must be identical for all of the issued addresses.
• The plane select bit, BA[6], must be different for each issued address.
• The page address bits, PA[5:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following two-plane program page
and erase block operations on a single die (LUN).
90
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x8, x16 NAND Flash Memory
Two-Plane Operations
© 2009 Micron Technology, Inc. All rights reserved.

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