DEMO9RS08KA2 Freescale Semiconductor, DEMO9RS08KA2 Datasheet - Page 103

• Manufacturer Part Number: DEMO9RS08KA2
• Description: DEMO BOARD FOR 9RS08KA2
• Manufacturer: Freescale Semiconductor
• Series: RS08r
• Type: MCUr

Specifications of DEMO9RS08KA2

• Contents: Board, Cable, CD, Documentation, Sample ICs
• Processor To Be Evaluated: RS08KA2
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: RS08
• Core Sub-architecture: RS08
• Silicon Core Number: MC9RS08
• Silicon Family Name: RS08KA
• Rohs Compliant: Yes
• For Use With/related Products: MC9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Active BDM:
12.4
The BDC contains two non-CPU accessible registers:
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode. Also, the status bits (BDMACT, WS, and
WSF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC
command.
12.4.1
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
Freescale Semiconductor
BDMACT
Reset in
ENBDM
Normal
•
•
•
Field
Reset
7
6
W
Subsequent bits must occur within 512 BDC cycles of the last bit sent.
The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
The BDC breakpoint register (BDCBKPT) holds a 16-bit breakpoint match address.
R
BDC Registers and Control Bits
BDC Status and Control Register (BDCSCR)
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it
required
0 BDM cannot be made active (non-intrusive commands still allowed).
1 BDM can be made active to allow active background mode commands.
Background Mode Active Status — This is a read-only status bit
0 BDM not active (user application program running).
1 BDM active and waiting for serial commands.
0
1
7
.
= Unimplemented or Reserved
.
BDMACT
Figure 12-6. BDC Status and Control Register (BDCSCR)
If the application can go into stop mode, this bit is required to be set if debugging capabilities are
0
1
6
Table 12-1. BDCSCR Register Field Descriptions
MC9RS08KA2 Series Data Sheet, Rev. 4
BKPTEN
0
0
5
FTS
4
0
0
Description
0
0
0
3
.
WS
0
0
2
Chapter 12 Development Support
WSF
0
0
1
0
0
0
0
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