DEMO9RS08KA2 Freescale Semiconductor, DEMO9RS08KA2 Datasheet - Page 36

• Manufacturer Part Number: DEMO9RS08KA2
• Description: DEMO BOARD FOR 9RS08KA2
• Manufacturer: Freescale Semiconductor
• Series: RS08r
• Type: MCUr

Specifications of DEMO9RS08KA2

• Contents: Board, Cable, CD, Documentation, Sample ICs
• Processor To Be Evaluated: RS08KA2
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: RS08
• Core Sub-architecture: RS08
• Silicon Core Number: MC9RS08
• Silicon Family Name: RS08KA
• Rohs Compliant: Yes
• For Use With/related Products: MC9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Resets, Interrupts, and General System Control
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).
5.4
The COP watchdog is intended to force a system reset if the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT, which enables the COP watchdog (see
“System Options Register
application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the
address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this
address is decoded and sends a reset signal to the COP counter.
There is an associated short and long time-out controlled by COPT in SOPT.
control functions of the COPT bit. The COP watchdog operates from the 1-kHz clock source and defaults
to the associated long time-out (2
Even if the application will use the reset default settings of COPE and COPT, the user should write to the
write-once SOPT registers during reset initialization to lock in the settings. That way, they cannot be
changed accidentally if the application program gets lost. The initial write to SOPT will reset the COP
counter.
In background debug mode, the COP counter will not increment.
When the MCU enters stop mode, the COP counter is re-initialized to zero upon entry to stop mode. The
COP counter begins from zero as soon as the MCU exits stop mode.
5.5
The MC9RS08KA2 Series does not include an interrupt controller with vector table lookup mechanism as
used on the HC08 and HCS08 devices. However, the interrupt sources from modules such as LVD, KBI,
36
•
•
•
•
Computer operating properly (COP) timer
Illegal opcode detect (ILOP)
Illegal address detect (ILAD)
Background debug forced reset via BDC command BDC_RESET
Computer Operating Properly (COP) Watchdog
Interrupts
(SOPT),” for additional information). If the COP watchdog is not used in an
1
Values shown in this column are based on
t
Timing,” for the tolerance of this value.
RTI
8
Table 5-1. COP Configuration Options
cycles).
MC9RS08KA2 Series Data Sheet, Rev. 4
COPT
≈ 1 ms. See t
0
1
RTI
in the
COP Overflow Count
2
2
8
5
Section A.9.1, “Control
cycles (256 ms)
cycles (32 ms)
1
Table 5-1
Freescale Semiconductor
summaries the
Section 5.8.2,