DEMO9RS08KA2 Freescale Semiconductor, DEMO9RS08KA2 Datasheet - Page 40

• Manufacturer Part Number: DEMO9RS08KA2
• Description: DEMO BOARD FOR 9RS08KA2
• Manufacturer: Freescale Semiconductor
• Series: RS08r
• Type: MCUr

Specifications of DEMO9RS08KA2

• Contents: Board, Cable, CD, Documentation, Sample ICs
• Processor To Be Evaluated: RS08KA2
• Data Bus Width: 8 bit
• Interface Type: USB
• Silicon Manufacturer: Freescale
• Core Architecture: RS08
• Core Sub-architecture: RS08
• Silicon Core Number: MC9RS08
• Silicon Family Name: RS08KA
• Rohs Compliant: Yes
• For Use With/related Products: MC9RS08KA2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Resets, Interrupts, and General System Control
1
2
5.8.3
These high page read-only registers are included so host development systems can identify the RS08
derivative and revision number. This allows the development software to recognize where specific
memory blocks, registers, and control bits are located in a target MCU.
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
40
BKGDPE
When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is
disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active
BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.
BKGDPE can only write once from value 1 to 0. Writing from value 0 to 1 by user software is not allowed. BKGDPE can be
changed back to 1 only by a POR or reset with proper condition as stated in Note 1.
Reset:
STOPE
RSTPE
COPE
COPT
Field
7
6
5
1
0
W
R
1,2
0 (Note 1)
REV3
System Device Identification Register (SDIDH, SDIDL)
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA3/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA3/ACMPO/BKGD/MS pin functions as PTA3 or ACMPO.
1 PTA3/ACMPO/BKGD/MS pin functions as BKGD/MS.
RESET Pin Enable — When set, this write-once bit enables the PTA2/KBIP2/TCLK/RESET/V
as RESET. When clear, the pin functions as one of its input-only alternative functions. This pin is input-only port
function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTA2/KBIP2/TCLK/RESET/V
1 PTA2/KBIP2/TCLK/RESET/V
7
Figure 5-3. System Device Identification Register — High (SDIDH)
= Unimplemented or Reserved
0 (Note 1)
REV2
6
Table 5-3. SOPT Register Field Descriptions
0 (Note 1)
MC9RS08KA2 Series Data Sheet, Rev. 4
REV1
5
PP
PP
pin functions as PTA2/KBIP2/TCLK/V
pin functions as RESET/V
0 (Note 1)
REV0
4
Description
ID11
1
3
PP
.
PP
ID10
.
0
2
Freescale Semiconductor
ID9
0
1
PP
pin to function
ID8
0
0