DEMO9RS08KA2 Freescale Semiconductor, DEMO9RS08KA2 Datasheet - Page 80

DEMO BOARD FOR 9RS08KA2

DEMO9RS08KA2

Manufacturer Part Number
DEMO9RS08KA2
Description
DEMO BOARD FOR 9RS08KA2
Manufacturer
Freescale Semiconductor
Series
RS08r
Type
MCUr

Specifications of DEMO9RS08KA2

Contents
Board, Cable, CD, Documentation, Sample ICs
Processor To Be Evaluated
RS08KA2
Data Bus Width
8 bit
Interface Type
USB
Silicon Manufacturer
Freescale
Core Architecture
RS08
Core Sub-architecture
RS08
Silicon Core Number
MC9RS08
Silicon Family Name
RS08KA
Rohs Compliant
Yes
For Use With/related Products
MC9RS08KA2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9RS08KA2
Manufacturer:
Freescale Semiconductor
Quantity:
135
Internal Clock Source (RS08ICSV1)
9.4
9.4.1
The states of the ICS are shown as a state diagram and are described in this section. The arrows indicate
the allowed movements between the states.
9.4.1.1
FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when CLKS is
written to 0.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency.
9.4.1.2
The FLL bypassed internal (FBI) mode is entered when CLKS is written to 1 and LP bit is a 0.
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the filter frequency.
9.4.1.3
The FLL bypassed internal low power (FBILP) mode is entered when CLKS is written to 1 and LP = 1.
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled.
80
Functional Description
1
2
was active before MCU entered stop, unless a reset occurs while in stop.
ICS enters its Stop state when MCU enters stop, FLL is always disabled. ICS returns to the state that
If IREFSTEN is set when MCU enters stop, the ICSIRCLK remains running.
Operational Modes
FLL Engaged Internal (FEI)
FLL Bypassed Internal (FBI)
FLL Bypassed Internal Low Power (FBILP)
FLL Engaged
Internal (FEI)
CLKS=0
MC9RS08KA2 Series Data Sheet, Rev. 4
Figure 9-7. Clock Switching Modes
FLL Bypassed
Internal (FBI)
CLKS=1
LP=0
Stop
1, 2
FLL Bypassed
Internal Low
Power(FBILP)
CLKS=1
LP=1
Freescale Semiconductor

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