DEMO9RS08KA2 Freescale Semiconductor, DEMO9RS08KA2 Datasheet - Page 76

DEMO BOARD FOR 9RS08KA2

DEMO9RS08KA2

Manufacturer Part Number
DEMO9RS08KA2
Description
DEMO BOARD FOR 9RS08KA2
Manufacturer
Freescale Semiconductor
Series
RS08r
Type
MCUr

Specifications of DEMO9RS08KA2

Contents
Board, Cable, CD, Documentation, Sample ICs
Processor To Be Evaluated
RS08KA2
Data Bus Width
8 bit
Interface Type
USB
Silicon Manufacturer
Freescale
Core Architecture
RS08
Core Sub-architecture
RS08
Silicon Core Number
MC9RS08
Silicon Family Name
RS08KA
Rohs Compliant
Yes
For Use With/related Products
MC9RS08KA2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9RS08KA2
Manufacturer:
Freescale Semiconductor
Quantity:
135
Internal Clock Source (RS08ICSV1)
9.1.1
Key features of the ICS module are:
9.1.2
There are four modes of operation for the ICS: FEI, FBI, FBILP, and stop.
9.1.2.1
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock.
9.1.2.2
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock.
9.1.2.3
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock.
9.1.2.4
In stop mode, the FLL is disabled and the internal reference clocks can be selected to be enabled or
disabled. The ICS does not provide an MCU clock source.
9.1.3
Figure 9-2
76
Frequency-locked loop (FLL) is trimmable for accuracy
— 0.2% resolution using internal 32 kHz reference
— 2% deviation over voltage and temperature using internal 32 kHz reference
— DCO output is 512 times internal reference frequency
Internal reference clock has 9 trim bits available
Internal reference clock can be selected as the clock source for the MCU
Whichever clock is selected as the source can be divided down
— 2 bit select for clock divider is provided (allowable dividers are: 1, 2, 4, and 8)
FLL engaged internal mode is automatically selected out of reset
shows the ICS block diagram.
Features
Modes of Operation
Block Diagram
FLL Engaged Interna
FLL Bypassed Interna
FLL Bypassed Interna
Stop (STOP)
MC9RS08KA2 Series Data Sheet, Rev. 4
l (FEI)
l (FBI)
l Low Power (FBILP)
Freescale Semiconductor

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