82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 109

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.25 LINE DRIVER
impedance state immediately.
tion can be enabled. The driver’s output current (peak to peak) is limited
to 110 mA typically. When the output current exceeds the limitation, the
transmit driver failure will be captured by the DF_S bit. Selected by the
DF_IES bit, a transition from ‘0’ to ‘1’ on the DF_S bit or any transition
from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit will set the DF_IS bit.
When the DF_IS bit is ‘1’, an interrupt on the INT pin will be reported if
enabled by the DF_IE bit.
3.26 TRANSMITTER IMPEDANCE MATCHING
by using internal impedance matching circuit. 100 Ω, 110 Ω, 75 Ω or
120 Ω internal impedance matching circuit can be selected by the
T_TERM[1:0] bits. The external impedance circuitry is not supported in
T1/J1 mode.
using internal impedance matching circuit or external impedance
matching circuit. When the T_TERM[2] bit is ‘0’, the internal impedance
matching circuit is enabled. 100 Ω, 110 Ω, 75 Ω or 120 Ω internal
impedance matching circuit can be selected by the T_TERM[1:0] bits.
When the T_TERM[2] bit is ‘1’, the internal impedance matching circuit
is disabled, and different external resistors should be used to realize
different impedance matching.
Functional Description
IDT82P2288
The Line Driver can be set to High-Z for redundant application.
The following ways will set the drivers to High-Z:
By these ways, the TTIPn and TRINGn pins will enter into high
Controlled by the DFM_ON bit, the output driver short-circuit protec-
In T1/J1 mode, the transmitter impedance matching can be realized
In E1 mode, the transmitter impedance matching can be realized by
- Setting the THZ pin to high will globally set all the Line Drivers to
- When there is no clock input on the OSCI pin, all the Line Drivers
- After software reset, hardware reset or power on, all the Line
- Setting the T_HZ bit to ‘1’ will set the corresponding Line Driver
- In Transmit Clock Master mode, if the XTS bit is ‘1’, the source of
- In Transmit Clock Slave mode, if the XTS bit is ‘0’, the source of
- When the transmit path is power down, the Line Driver in the cor-
High-Z;
will be High-Z (no clock means this: the input on the OSCI pin is
in high/low level, or the duty cycle is less than 30% or larger than
70%);
Drivers will be High-Z;
to High-Z;
the transmit clock is from the recovered clock from the line side.
When the recovered clock from the line side is lost, the Line
Driver in the corresponding link will be High-Z;
the transmit clock is from the backplane timing clock. When the
backplane timing clock is lost (i.e., no transition for more than 72
T1/E1/J1 cycles), the Line Driver in the corresponding link will be
High-Z. However, there is an exception in this case. That is, if the
link is in Remote Loopback mode, the Line Driver will not be
High-Z.
responding link will be High-Z.
109
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
cable for one link. Table 75 lists the recommended impedance matching
values for the transmitter.
3.27 TESTING AND DIAGNOSTIC FACILITIES
3.27.1 PRBS GENERATOR / DETECTOR
transmit or receive direction, and detects the pattern in the opposite
direction. The direction is determined by the PRBSDIR bit. The pattern
can be generated or detected in unframed mode, in 8-bit-based mode or
in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the data streams are extracted or replaced
and the per-channel/per-TS configuration in the TEST bit is ignored. In
8-bit-based mode or in 7-bit-based mode, the extracted or replaced
channel/timeslot is specified by the TEST bit. (In 7-bit-based mode, only
the higher 7 bits of the selected channel/timeslot are used for PRBS
test).
Table 75: Impedance Matching Value For The Transmitter
Table 76: Related Bit / Register In Chapter 3.25 & Chapter 3.26
Configuration
Figure 2 shows the appropriate components to connect with the
120 Ω (E1)
100 Ω (T1)
The PRBS Generator / Detector generates test pattern to either the
110 Ω (J1)
75 Ω (E1)
T_TERM[2:0]
Cable
DFM_ON
DF_IES
DF_IS
DF_IE
DF_S
T_HZ
XTS
Bit
T_TERM[2:0]
Internal Termination
Interrupt Trigger Edges Select
Transmit And Receive Termi-
0 0 0
0 0 1
0 1 0
0 1 1
Interrupt Enable Control 0
Transmit Configuration 1
Transmit Timing Option
Line Status Register 0
nation Configuration
Interrupt Status 0
Register
0 Ω
R
T
T_TERM[2:0]
External Termination
JANUARY 10, 2011
1 X X
03A, 13A, 23A, 33A,
43A, 53A, 63A, 73A
023, 123, 223, 323,
070, 170, 270, 370,
036, 136, 236, 336,
035, 135, 235, 335,
033, 133, 233, 333,
032, 132, 232, 332,
-
-
423, 523, 623, 723
470, 570, 670, 770
436, 536, 636, 736
435, 535, 635, 735
433, 533, 633, 733
432, 532, 632, 732
Address (Hex)
9.4 Ω
R
-
-
T