82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 82

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

pin and the framing pulse on the TSFSn pin to input the data on the
TSDn pin are provided by the system side. When the TSLVCK bit is set
to ‘0’, each link uses its own TSCKn and TSFSn; when the TSLVCK bit
is set to ‘1’ and all eight links are in the Transmit Clock Slave mode, the
eight links use the TSCK[1] and TSFS[1] to input the data. The signaling
bits on the TSIGn pin are per-channel aligned with the data on the TSDn
pin.
is clocked by the TSCKn. The active edge of the TSCKn used to sample
the pulse on the TSFSn is determined by the FE bit. The active edge of
the TSCKn used to sample the data on the TSDn and TSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the TSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the TSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If all eight links use the
TSCK[1] and TSFS[1] to input the data, the CMS bit of the eight links
should be set to the same value. If the speed of the TSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
Functional Description
IDT82P2288
2.048
1.544
1.544
2.048
Mb/s
Mb/s
Mb/s
Mb/s
In the Transmit Clock Slave mode, the timing signal on the TSCKn
In the Transmit Clock Slave mode, the data on the system interface
discarded
discarded
F
TS0
TS0
the 8th bit
the 8th bit
F
CH1
CH1
TS1
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode
TS1
CH2
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode
TS2
CH2
TS2
CH3
TS3
TS3
CH3
discarded
CH4
TS4
CH5
TS5
TS6
CH6
TS23
CH23
TS7
CH7
TS24
discarded
82
TS8
CH24
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the EDGE bit determines the active edge to sample the data on the
TSDn and TSIGn pins. The pulse on the TSFSn pin is always sampled
on its first active edge.
or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The indica-
tions are selected by the FSTYP bit. The active polarity of the TSFSn is
selected by the FSINV bit. If the pulse on the TSFSn pin is not an integer
multiple of 125 µs, this detection will be indicated by the TCOFAI bit. If
the TCOFAE bit is enabled, an interrupt will be reported by the INT pin
when the TCOFAI bit is ‘1’.
3.18.1.3 Transmit Multiplexed Mode
on the system side (2.048 Mb/s) should be mapped to the data rate in
the line side (1.544 Mb/s), 3 kinds of schemes should be selected by the
MAP[1:0] bits. The schemes per G.802, per One Filler Every Four CHs
and per Continuous CHs are the same as the description in
Chapter 3.18.1.2 Transmit Clock Slave Mode.
transmit the data to all eight links. The data of Link 1 to Link 4 is byte-
interleaved input from the multiplexed bus 1, while the data of Link 5 to
Link 8 is byte-interleaved input from the multiplexed bus 2. When the
discarded
In the Transmit Clock Slave mode, the TSFSn can indicate each F-bit
In the Transmit Multiplexed mode, since the demultiplexed data rate
In the Transmit Multiplexed mode, two multiplexed buses are used to
TS25~TS31
TS9
F
CH1
discarded
CH22
discarded
TS28 TS29 TS30 TS31
TS0
CH2
CH23
the 8th bit
TS1
CH24
TS2
discarded
F
CH1
CH24
JANUARY 10, 2011
TS0
the 8th bit
CH2
F CH1
TS1
TS24