82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 76

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

bits and the TSOFF[6:0] bits are not ‘0’ respectively.
the corresponding frame output on the RSDn/MRSDA(MRSDB) pin will
delay ‘N’ clock cycles to the framing pulse on the RSFSn/MRSFS pin.
(Here ‘N’ is defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and
the TSOFF[6:0] bits are set, the start of the corresponding frame output
on the RSDn/MRSDA(MRSDB) pin will delay ‘8 x M’ clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here ‘M’ is defined by the
TSOFF[6:0].)
BOFF[2:0] bits are set, the start of the corresponding frame output on
the RSDn/MRSDA(MRSDB) pin will delay ‘2 x N’ clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here ‘N’ is defined by the
BOFF[2:0] bits.) When the CMS bit is ‘1’ (i.e., in double clock mode) and
Functional Description
IDT82P2288
The bit offset and channel offset are configured when the BOFF[2:0]
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
Receive Clock Slave mode / Receive Multiplexed mode:
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
RSDn / MRSDA(B)
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path
FE = 1, DE = 0
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
76
F-bit (T1/J1)
F-bit (T1/J1)
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the TSOFF[6:0] bits are set, the start of the corresponding frame output
on the RSDn/MRSDA(MRSDB) pin will delay ‘16 x M’ clock cycles to the
framing pulse on the RSFSn/MRSFS pin. (Here ‘M’ is defined by the
TSOFF[6:0].)
0 to 23 channels (0 & 23 are included). In Multiplexed mode, the channel
offset can be configured from 0 to 127 channels (0 & 127 are included).
3.17.1.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/
MRSIGA(MRSIGB)
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
In Non-multiplexed mode, the channel offset can be configured from
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
Bit 1 of CH1(T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1(T1/J1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
JANUARY 10, 2011