82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 344

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table 85: TAP Controller State Description (Continued)
IEEE STD 1149.1 JTAG Test Access Port
IDT82P2288
Select-IR-
Update-IR The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the
Pause-IR
Exit2-DR
Capture-
Update-
Exit1-IR
Exit2-IR
Shift-IR
Pause-
State
Scan
DR
DR
IR
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO.
For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data
register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this
state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAM-
PLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output
of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-reg-
ister stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state.
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising
edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If
TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this
state.
In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports fault-
isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change
during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or
the Shift-IR state if TMS is held low.
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output
on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change dur-
ing this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or
remains in the Shift-IR state if TMS is held low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the
current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is
low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous
value.
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Description
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
JANUARY 10, 2011