82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 71

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.17 RECEIVE SYSTEM INTERFACE
data stream to the system backplane. The data from the eight links can
be aligned with each other or be output independently. The timing clocks
and framing pulses can be provided by the system backplane or
obtained from the far end. The Receive System Interface supports
various configurations to meet various requirements in different applica-
tions.
3.17.1 T1/J1 MODE
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSDn pin is used to output the received data from each link at the bit
rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the
Multiplexed Mode, the received data from the eight links is converted to
2.048 Mb/s format and byte interleaved to form two high speed data
streams and output on the MRSDA1 (MRSDB1) and MRSDA2
(MRSDB2) pins at the bit rate of 8.192 Mb/s.
Table 39: Operating Modes Selection In T1/J1 Receive Path
Functional Description
IDT82P2288
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
3. In Receive Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided. Their functions are the same. One is the backup for the other.
RMUX
The Receive System Interface determines how to output the received
In T1/J1 mode, the Receive System Interface can be set in Non-
0
1
RMOD
E
X
0
1
G56K, GAP
/ FBITGAP
not all 0s
00 / 0
X
X
1
MAP[1:0]
00
01
10
01
10
11
11
X
2
Receive Clock Master Full T1/J1
Receive Clock Master Fractional T1/J1
Receive Clock Slave - T1/J1 Rate
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four
CHs
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
Operating Mode
71
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
(M)RSCKn/(M)RSFSn, and this clock is derived from line side signal or
MCLK (When LOSS).
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCKn, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
from outside. To avoid shatter data, this clock should keep the source
same with line side. If the backplane data rate is 2.048 Mbit/s, and the
Receive System Interface is in T1 mode E1 rate, the receive data (1.544
Mb/s) should be mapped to 2.048 Mb/s and there are 3 kinds of
mapping schemes.
eight links should be converted to 2.048 Mb/s format first and then multi-
plexed to 8.192 Mb/s, there are still 3 kinds of schemes to be selected.
each link into various operating modes and the pins’ direction of the
Receive System Interface in different operating modes.
In the Receive Clock Master mode, the device outputs clock
In the Receive Clock Master mode, if RSCKn outputs pulses during
In the Receive Clock Slave mode, clock (M)RSCKn/(M)RSFSn is
In the Receive Multiplexed mode, since the received data from the
Table 39 summarizes how to set the Receive System Interface of
RSCKn, RSFSn
Receive System Interface Pin
MRSCK,
MRSFS
Input
X
JANUARY 10, 2011
RSCKn, RSFSn,
MRSIGB[1:2])
RSDn, RSIGn
RSDn, RSIGn
(MRSDB[1:2],
MRSDA[1:2],
MRSIGA[1:2]
Output
3