82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 78

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The speed of the RSCKn can be selected by
the CMS bit to be the same rate as the data rate on the system side
(2.048 MHz) or double the data rate (4.096 MHz). If all eight links use
the RSCK[1] and RSFS[1] to output the data, the CMS bit of the eight
links should be set to the same value. If the speed of the RSCKn is
double the data rate, there will be two active edges in one bit duration. In
this case, the EDGE bit determines the active edge to update the data
on the RSDn and RSIGn pins. The pulse on the RSFSn pin is always
sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.3 Receive Multiplexed Mode
output the data from all eight links. The data of Link 1 to Link 4 is byte-
interleaved output on the multiplexed bus 1, while the data of Link 5 to
Link 8 is byte-interleaved output on the multiplexed bus 2. When the
data from the four links is output on one multiplexed bus, the sequence
of the data is arranged by setting the timeslot offset. The data from
different links on one multiplexed bus must be shifted at a different
timeslot offset to avoid data mixing.
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all eight links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-timeslot aligned with the corresponding data on
the MRSDA (MRSDB) pin.
clocked by the MRSCK. The active edge of the MRSCK used to sample
the pulse on the MRSFS is determined by the FE bit. The active edge of
the MRSCK used to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the DE
Functional Description
IDT82P2288
In the Receive Clock Slave mode, the data on the system interface is
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
In the Receive Multiplexed mode, two multiplexed buses are used to
In the Receive Multiplexed mode, the timing signal on the MRSCK
In the Receive Multiplexed mode, the data on the system interface is
78
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
bit of the eight links should be set to the same value respectively. If the
FE bit and the DE bit are not equal, the pulse on the MRSFS is ahead.
The MRSCK can be selected by the CMS bit to be the same rate as the
data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the eight links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
eight links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125 µs, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4 Offset
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFSn/MRSFS
pin and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB)
MRSIGA(MRSIGB) pin are always per-timeslot aligned with the data on
the RSDn/MRSDA(MRSDB) pin.
different operating modes and the configuration of the offset.
0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot
offset can be configured from 0 to 127 timeslots (0 & 127 are included).
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/
MRSIGA(MRSIGB)
MRSIGA(MRSIGB) pins can be configured by the TRI bit of the corre-
sponding link to be in high impedance state or to output the processed
data stream.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Except that in the Receive Master mode, when the OHD bit, the
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured from
The output on the RSDn/MRSDA(MRSDB) and the RSIGn/
pin.
The
signaling
bits
JANUARY 10, 2011
on
the
RSIGn/