82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 77

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.17.2 E1 MODE
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSDn pin is used to output the received data from each link at the bit
rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data
from the eight links is byte interleaved to form two high speed data
streams and output on the MRSDA1 (MRSDB1) and MRSDA2
(MRSDB2) pins at the bit rate of 8.192 Mb/s.
receive system interface is in Receive Clock Slave mode, otherwise if
the device outputs RSCK, the receive system interface is in Receive
Clock Master mode.
3.17.2.1 Receive Clock Master Mode
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
timeslot aligned with the data on the RSDn pin.
is clocked by the RSCKn. The active edge of the RSCKn used to update
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead.
Basic frame, CRC Multi-frame, Signaling Multi-frame, or both the CRC
Multi-frame and Signaling Multi-frame, or the TS1 and TS 16 overhead.
All the indications are selected by the OHD bit, the SMFS bit and the
CMFS bit. The active polarity of the RSFSn is selected by the FSINV bit.
Clock Master Full E1 mode and Receive Clock Master Fractional E1
mode.
Table 40: Operating Modes Selection In E1 Receive Path
Functional Description
IDT82P2288
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. In Receive Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided. Their functions are the same. One is the backup for the other.
RMUX RMODE
In E1 mode, the Receive System Interface can be set in Non-multi-
In the Non-multiplexed mode, if the RSCK is from outside, the
In the Receive Clock Master mode, each link uses its own timing
In the Receive Clock Master mode, the data on the system interface
In the Receive Clock Master mode, the RSFSn can indicate the
The Receive Clock Master mode includes two sub-modes: Receive
0
1
X
0
1
not both 0s
G56K, GAP
00
X
X
1
Receive Clock Master Full E1
Receive Clock Master Fractional E1
Receive Clock Slave
Receive Multiplexed
Operating Mode
MRSCK, MRSFS
RSCKn, RSFSn
77
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the entire E1 frame, the Receive System Interface is in Receive Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on RSCKn, the Receive System Interface is in Receive Clock
Master Fractional E1 mode.
link into various operating modes and the pins’ direction of the receive
system interface in different operating modes.
Receive Clock Master Full E1 Mode
Master mode, the special feature in this mode is that the RSCKn is a
standard 2.048 MHz clock, and the data in all 32 timeslots in a standard
E1 frame is clocked out by the RSCKn.
Receive Clock Master Fractional E1 Mode
Master mode, the special feature in this mode is that the RSCKn is a
gapped 2.048 MHz clock (no clock signal during the selected timeslot).
selecting the G56K & GAP bits in the Receive Payload Control. The data
in the corresponding gapped duration is a don't care condition.
3.17.2.2 Receive Clock Slave Mode
pin and framing pulse on the RSFSn pin to output the data on the RSDn
pin are provided by the system side. When the RSLVCK bit is set to ‘0’,
each link uses its own RSCKn and RSFSn; when the RSLVCK bit is set
to ‘1’ and all eight links are in the Receive Clock Slave mode, the eight
links use the RSCK[1] and RSFS[1] to output the data. The signaling bits
on the RSIGn pin are per-timeslot aligned with the data on the RSDn
pin.
Input
X
Besides all the common functions described in the Receive Clock
Besides all the common functions described in the Receive Clock
The RSCKn is gapped during the timeslots or the Bit 8 duration by
In the Receive Clock Slave mode, the timing signal on the RSCKn
In the Receive Clock Master mode, if RSCKn outputs pulses during
Table 40 summarizes how to set the receive system interface of each
MRSDA[1:2], MRSIGA[1:2] (MRSDB[1:2], MRSIGB[1:2])
Receive System Interface Pin
RSCKn, RSFSn, RSDn, RSIGn
RSDn, RSIGn
Output
JANUARY 10, 2011
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