82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 96

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.20.3 AUTOMATIC PERFORMANCE REPORT MESSAGE (T1/J1
ONLY)
transmitted in the ESF format in T1/J1 mode.
No. 1 to Octet No. 14. In the above table, the value in the C/R bit posi-
tion, the R bit position, the U1 bit position, the U2 bit position and the LB
bit position are determined by the CRBIT bit, the RBIT bit, the U1BIT bit,
the U2BIT bit and the LBBIT bit in the APRM Control register respec-
tively.
Table 53: APRM Message Format
Functional Description
IDT82P2288
The Automatic Performance Report Message (APRM) can only be
Five kinds of events are counted every second in the APRM:
• The Bipolar Violation (BPV) Error / HDB3 Code Violation (CV)
• The CRC-6 Error event detected in the Frame Processor;
The APRM is transmitted bit by bit from Bit 1 to Bit 8 and from Octet
Error event detected in the B8ZS/HDL3/AMI Decoder;
Octet No.
10
12
13
14
11
1
2
3
4
5
6
7
8
9
Bit 8
G3
FE
G3
FE
G3
FE
G3
FE
Bit 7
SE
SE
SE
SE
LV
LV
LV
LV
Bit 6
G4
LB
G4
LB
G4
LB
G4
LB
96
Bit 5
SAPI (‘001110C/R0’)
G1
Control (‘00000011’)
U1
G1
U1
G1
U1
G1
U1
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Message is generated every one second and transmitted on the DL bit
positions. The APRM format is illustrated in Table 53.
numbers counted by the APRM. The details are listed in Table 54. Their
default value are ‘0’s.
Flag (‘01111110’)
TEI (‘00000001’)
• The Frame Alignment Bit Error event detected in the Frame Pro-
• The Severely Frame Alignment Bit Error event detected in the
• The Buffer Slip event occurred in the Elastic Store Buffer.
Enabled by the AUTOPRM bit, the Automatic Performance Report
The Nm and Ni bit position is a module 4 counter.
The remaining bits in Octet No.5 to Octet No. 12 interpret the event
cessor;
Frame Processor;
FCS
Bit 4
U2
U2
U2
U2
R
R
R
R
Bit 3
G5
G2
G5
G2
G5
G2
G5
G2
Bit 2
Nm
Nm
Nm
Nm
SL
SL
SL
SL
JANUARY 10, 2011
Bit 1
G6
G6
G6
G6
Ni
Ni
Ni
Ni