82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 74

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

of the data is arranged by setting the channel offset. The data from
different links on one multiplexed bus must be shifted at a different
channel offset to avoid data mixing.
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to all eight links. The signaling bits on the MRSIGA
(MRSIGB) pin are per-channel aligned with the corresponding data on
the MRSDA (MRSDB) pin.
clocked by the MRSCK. The active edge of the MRSCK used to sample
the pulse on the MRSFS is determined by the FE bit. The active edge of
the MRSCK used to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) is determined by the DE bit. The FE bit and the DE
bit of the eight links should be set to the same value respectively. If the
FE bit and the DE bit are not equal, the pulse on the MRSFS is ahead.
The MRSCK can be selected by the CMS bit to be the same rate as the
data rate on the system side (8.192 MHz) or double the data rate
(16.384 MHz). The CMS bit of the eight links should be set to the same
value. If the speed of the MRSCK is double the data rate, there will be
two active edges in one bit duration. In this case, the EDGE bit deter-
Functional Description
IDT82P2288
In the Receive Multiplexed mode, the timing signal on the MRSCK
In the Receive Multiplexed mode, the data on the system interface is
Receive Clock Slave mode / Receive Multiplexed mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Receive Clock Master mode:
RSFSn / MRSFS
RSCKn / MRSCK
RSDn / MRSDA(B)
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
FE = 1, DE = 1
F-bit (T1/J1)
F-bit (T1/J1)
74
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
mines the active edge to update the data on the MRSDA (MRSDB) and
MRSIGA (MRSIGB) pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
eight links should be set to the same value. If the pulse on the MRSFS
pin is not an integer multiple of 125 µs, this detection will be indicated by
the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be
reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.4 Offset
modes. The offset is between the framing pulse on RSFSn/MRSFS pin
and the start of the corresponding frame output on the RSDn/
MRSDA(MRSDB)
MRSIGA(MRSIGB) pin are always per-channel aligned with the data on
the RSDn/MRSDA(MRSDB) pin.
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Bit offset and channel offset are both supported in all the operating
Figure 21 to Figure 24 show the base line without offset.
Bit 1 of CH1(T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1(T1/J1)
Bit 2 of TS0 (E1)
pin.
The
signaling
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
bits
JANUARY 10, 2011
on
the
RSIGn/