82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 340

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table 82: IR Code
6.2
6.2.1
facturer Identity and a fixed bit. The IDR is 32 bits long and is partitioned
as in Table 83. Data from the IDR is shifted out to the TDO LSB first.
6.2.2
the TDI input and TDO output, bypassing the BYR to reduce test access
times.
Table 83: IDR
IEEE STD 1149.1 JTAG Test Access Port
IDT82P2288
Code
0 0 0
0 1 0
0 0 1
1 1 1
0 1 1
0 1 0
1 0 1
The IDR can be set to define the Vision, the Part Number, the Manu-
The BYR consists of a single bit. It can provide a serial path between
IR
JTAG DATA REGISTER
DEVICE IDENTIFICATION REGISTER (IDR)
BYPASS REGISTER (BYP)
12 ~ 27
28 ~ 31
Bit No.
1 ~ 11
Instruction
PRELOAD
SAMPLE /
0
EXTEST
IDCODE
BYPASS
CLAMP
HIGHZ
-
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction,
the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by loading the boundary scan
register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR
state. The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the boundary scan register
using the Update-DR state.
The sample/preload instruction is used to allow scanning of the boundary-scan register without causing interference to the normal opera-
tion of the on-chip system logic. Data received at system input pins is supplied without modification to the on-chip system logic; data from
the on-chip system logic is driven without modification through the system output pins. SAMPLE allows a snapshot to be taken of the data
flowing from the system pins to the on-chip system logic or vice versa, without interfering with the normal operation of the assembled
board. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of boundary-scan register cells prior to selec-
tion of another boundary-scan test operation.
The identification instruction is used to connect the identification register between TDI and TDO. The device’s identification code can then
be shifted out using the Shift-DR state.
The BYPASS instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the
device.
This instruction allows the state of the signals driven from device pins to be determined from the boundary-scan register while the bypass
register is selected as the serial path between TDI and TDO. The signals driven from the device pins will not change while the CLAMP
instruction is selected.
Use of the HIGHZ instruction places the device in a state in which all of its system logic outputs are placed in an inactive drive state (e.g.,
high impedance). In this state, and in-circuit test system may drive signals onto the connections normally driven by a device output with-
out incurring the risk of damage to the device.
(for IC manufactory test)
Manufacturer Identity (033H)
Part Number (04D7H)
Version Number
Comments
Set to ‘1’
340
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
6.2.3
Table 84: Boundary Scan (BS) Sequence
The bidirectional ports interface to 2 boundary scan cells:
- In cell: The Input cell is observable only (BC_4).
- Out cell: The output cell is controllable and observable (BC_1).
The Boundary Scan (BS) sequence is illustrated in Table 84.
Comment
BOUNDARY SCAN REGISTER (BSR)
CLE_GEN_2.048
CLE_GEN_1.544
BS-Cell Name
CLK_SEL[0]
CLK_SEL[1]
REFB_OUT
REFA_OUT
THZ
IC
IC
BS No.
173
172
171
170
169
168
167
166
165
JANUARY 10, 2011
BS-Cell Type
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL