82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 73

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

pin and the framing pulse on the RSFSn pin to output the data on the
RSDn pin are provided by the system side. When the RSLVCK bit is set
to ‘0’, each link uses its own RSCKn and RSFSn; when the RSLVCK bit
is set to ‘1’ and all eight links are in the Receive Clock Slave mode, the
eight links use the RSCK[1] and RSFS[1] to output the data. The
signaling bits on the RSIGn pin are per-channel aligned with the data on
the RSDn pin.
clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The data rate of the system side is 1.544 Mb/s
or 2.048 Mb/s. When it is 2.048 Mb/s, the RSCKn can be selected by the
CMS bit to be the same rate as the data rate on the system side (2.048
MHz) or double the data rate (4.096 MHz). If all eight links use the
RSCK[1] and RSFS[1] to output the data, the CMS bit of the eight links
should be set to the same value. If the speed of the RSCKn is double the
data rate, there will be two active edges in one bit duration. In this case,
Functional Description
IDT82P2288
1.544
2.048
1.544
2.048
Mb/s
Mb/s
Mb/s
Mb/s
In the Receive Clock Slave mode, the timing signal on the RSCKn
In the Receive Clock Slave mode, the data on the system interface is
filler
filler
F
TS0
TS0
the 8th bit
the 8th bit
F
CH1
CH1
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode
TS1
TS1
CH2
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode
TS2
CH2
TS2
CH3
TS3
TS3
CH3
CH4
TS4
filler
CH5
TS5
TS6
CH6
TS23
CH23
TS7
CH7
TS24
73
TS8
filler
CH24
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
the EDGE bit determines the active edge to update the data on the
RSDn and RSIGn pins. The pulse on the RSFSn pin is always sampled
on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.3 Receive Multiplexed Mode
eight links should be mapped to 2.048 Mb/s format first, the 3 kinds of
schemes should be selected by the MAP[1:0] bits. The mapping per
G.802, per One Filler Every Four CHs and per Continuous CHs are the
same as the description in Chapter 3.17.1.2 Receive Clock Slave Mode.
output the data from all eight links. The data of Link 1 to Link 4 is byte-
interleaved output on the multiplexed bus 1, while the data of Link 5 to
Link 8 is byte-interleaved output on the multiplexed bus 2. When the
data from the four links is output on one multiplexed bus, the sequence
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
In the Receive Multiplexed mode, since the received data from the
In the Receive Multiplexed mode, two multiplexed buses are used to
TS25~TS31
TS9
filler
F
CH1
CH22
filler
TS28 TS29 TS30 TS31
TS0
filler
the 8th bit
CH2
CH23
TS1
CH24
TS2
F
CH1
filler
CH24
JANUARY 10, 2011
TS0
the 8th bit
CH2
F CH1
TS1
TS24