82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 27

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.3
to intersymbol interference caused by cable attenuation and distortion.
Usually, the Adaptive Equalizer is off in short haul applications and is on
in long haul applications, which is configured by the EQ_ON bit.
incoming signals during a selectable observation period. The observa-
tion period is selected by the UPDW[1:0] bits. A shorter observation
period allows quicker response to pulse amplitude variation, while a
longer observation period can minimize the possible overshoots.
adjusted to achieve a normalized signal. The LATT[4:0] bits indicate the
signal attenuation introduced by the cable in approximately 2 dB per
step.
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4
3.5
from the received data. It is accomplished by Digital Phase Locked Loop
(DPLL). The recovered clock tracks the jitter in the data output from the
Data Slicer and keeps the phase relationship between data and clock
during the absence of the incoming pulse.
REFB_OUT. These pins output a recovered clock from the Clock and
Data Recovery function block of one of the eight links. The link is
selected by the RO1[2:0] for REFA_OUT and with RO2[2:0] for
REFB_OUT.
tion) on the link selected for REFA_OUT/REFB_OUT, this pin outputs
MCLK (delivered from OSCI input) or a high level signal as selected by
the REFH_LOS bit.
3.6
or not. This selection is made by the RJA_E bit.
Figure 7.
Functional Description
IDT82P2288
The Adaptive Equalizer can remove most of the signal distortion due
The peak detector keeps on measuring the peak value of the
Based on the observed peak value for a period, the equalizer will be
The Clock and Data Recovery is used to recover the clock signal
SJET provides two reference clock outputs REFA_OUT and
When Loss of Signal (LOS) is detected
The Receive Jitter Attenuator of each link can be chosen to be used
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
ADAPTIVE EQUALIZER
CLOCK AND DATA RECOVERY
RECEIVE JITTER ATTENUATOR
REFH_LOS
UPDW[1:0]
SLICE[1:0]
LATT[4:0]
EQ_ON
Bit
(Chapter 3.7.3 LOS Detec-
Reference Clock Output Control
Receive Configuration 1
Receive Configuration 2
Line Status Register 1
Register
27
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
J1 and E1 modes. In long haul application, the receive sensitivity is -36
dB in T1/J1 mode or -43 dB in E1 mode.
3.4
space according to the amplitude of the input signals. The criteria of
mark or space generation are based on a selected ratio of the incoming
signal amplitude against the peak value detected during the observation
period. This ratio is selected by the SLICE[1:0] bits. The output of the
Data Slicer is forwarded to the Clock and Data Recovery unit.
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter
tolerance is expected, while the 32-bit FIFO is used in delay sensitive
applications.
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter whose
frequency is lower than the CF passes through the DPLL without any
attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or
1.26 Hz, as selected by the RJA_BW bit. In E1 applications, the CF of
Jittered Clock
In short haul application, the receive sensitivity is -10 dB in both T1/
The Data Slicer is used to generate a standard amplitude mark or a
The FIFO is used as a pool to buffer the jittered input data, then the
The DPLL is used to generate a de-jittered clock to clock out the data
Jittered Data
DATA SLICER
pointer
Figure 7. Jitter Attenuator
write
02A, 12A, 22A, 32A, 42A, 52A, 62A, 72A
03E, 13E, 23E, 33E, 43E, 53E, 63E, 73E
029, 129, 229, 329, 429, 529, 629, 729
037, 137, 237, 337, 437, 537, 637, 737
32/64/128
DPLL
FIFO
Address (Hex)
pointer
read
JANUARY 10, 2011
De-jittered Data
De-jittered Clock