82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 167

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

T1/J1 RBIF Option Register (046H, 146H, 246H, 346H, 446H, 546H, 646H, 746H)
FBITGAP:
DE:
(MRSDB) and MRSIGA (MRSIGB).
FE:
CMS:
is set to ‘1’), the bit of the eight links should be set to the same value.
TRI:
Programming Information
IDT82P2288
Bit Name
This bit is valid in Receive Clock Master mode.
= 0: The F-bit is not gapped.
= 1: The F-bit is gapped (no clock signal during the F-bit).
This bit selects the active edge of RSCKn to update the data on RSDn and RSIGn and the active edge of MRSCK to update the data on MRSDA
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the eight links should be set to the same value.
This bit selects the active edge of RSCKn to update/sample the pulse on RSFSn and the active edge of MRSCK to sample the pulse on MRSFS.
= 0: The falling edge is selected.
= 1: The rising edge is selected.
In Receive Multiplexed mode, the bit of the eight links should be set to the same value.
This bit is valid in Receive Clock Slave T1/J1 mode E1 rate and Receive Multiplexed mode.
= 0: The speed of the RSCKn/MRSCK is the same as the data rate on the system side (2.048 MHz / 8.192 MHz).
= 1: The speed of the RSCKn/MRSCK is double the data rate on the system side (4.096 MHz / 16.384 MHz).
In Receive Clock Slave T1/J1 mode E1 rate, if all eight links use the RSCK[1] and RSFS[1] to output the data (i.e., the RSLVCK bit (b, T1/J1-010H)
In Receive Multiplexed mode, the bit of the eight links should be set to the same value.
= 0: The processed data and signaling bits are output on the RSDn/MRSDA(MRSDB) pins and the RSIGn/MRSIGA(MRSIGB) pins respectively.
= 1: The output on the RSDn/MRSDA(MRSDB) pins and the RSIGn/MRSIGA(MRSIGB) pins are in high impedance.
Default
Bit No.
Type
7
Reserved
6
5
FBITGAP
R/W
4
0
167
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
R/W
DE
3
1
R/W
FE
2
1
CMS
R/W
1
0
JANUARY 10, 2011
R/W
TRI
0
1