82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 39

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

When one or more bits do not match its pattern (refer to Table 14), a
single error is generated. When this error number exceeds the ratio set
in the M2O[1:0] bits, it is out of synchronization. Then if the REFEN bit is
‘1’, the Frame Processor will start to search for synchronization again. If
the REFEN bit is ‘0’, no error can lead to reframe except for manually
setting. The manual reframe is executed by a transition from ‘0’ to ‘1’ on
the REFR bit. During out of synchronization state, the error event detec-
tion is suspended.
previous one, the change of frame alignment event is generated. This
event is captured by the COFAI bit and is forwarded to the Performance
Monitor.
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
in Frame (2n) (0<n<12 and n=36) are also counted separately. When the
number of either of them exceeds the ratio set in the M2O[1:0] bits, it is
out of synchronization. Then if the REFEN bit is ‘1’, the Frame
Processor will start to search for synchronization again. If the REFEN bit
is ‘0’, no error can lead to reframe except for manually setting. The
Functional Description
IDT82P2288
• DDS Pattern Error: The received 6-bit DDS in each CH24 is com-
The 6-bit DDS pattern and its following F-bit make up a 7-bit pattern.
Once resynchronized, if the new-found F bit position differs from the
In SLC-96 format, only one kind of error is detected:
• F Bit Error: The Ft bit in each odd frame and the Fs bit in Frame
Each unmatched Ft bit in the odd frame and each unmatched Fs bit
event. This error event is captured by the FERI bit and is for-
warded to the Performance Monitor.
pared with the DDS pattern - ‘0XX11101’ (MSB left and ‘X’ is not
cared). When one or more bits do not match the DDS pattern, a
single DDS pattern error event is generated. This error event is for-
warded to the Performance Monitor.
(2n) (0<n<12 and n=36) is compared with the expected one (refer
to Table 15). Each unmatched bit leads to a F-bit error event. This
error event is captured by the FERI bit and is forwarded to the Per-
formance Monitor.
39
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
manual reframe is executed by a transition from ‘0’ to ‘1’ on the REFR
bit. During out of synchronization state, the error event detection is
suspended.
previous one, the change of frame alignment event is generated. This
event is captured by the COFAI bit and is forwarded to the Performance
Monitor.
3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only)
and Switch bits are all extracted to the RDL0, RDL1 & RDL2 registers
respectively.
to ‘1’. Thus, the value in the RDL0, RDL1 & RDL2 registers are updated
if the received corresponding code is the same for 2 consecutive SLC-
96 frames. Whether de-bounced or not, a change indication will be set in
the SCCI bit, SCMI bit, SCAI bit and SCSI bit respectively if the corre-
sponding codes in the RDL0, RDL1 & RDL2 registers differ from the
previous ones.
SLC-96 synchronization state.
3.8.1.4 Interrupt Summary
When there are conditions meeting the interrupt sources, the corre-
sponding Status bit will be asserted high. When there is a transition
(from ‘1’ to ‘0’ or from ‘0’ to ‘1’) on the Status bit, the corresponding
Status Interrupt Indication bit will be set to ‘1’ (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to ‘1’
directly) and the Status Interrupt Indication bit will be cleared by writing
‘1’. A ‘1’ in the Status Interrupt Indication bit indicates an interrupt
occurred. The interrupt is reported by the INT pin if its Status Interrupt
Enable bit was set to ‘1’.
Once resynchronized, if the new-found F bit position differs from the
In SLC-96 format, the Concentrator bits, Maintenance bits, Alarm bits
All these extractions will be set to de-bounce if the SCDEB bit is set
The value in the RDL0, RDL1 & RDL2 registers is held during out of
The interrupt sources in this block are summarized in Table 16.
JANUARY 10, 2011