82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 9

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

List of Figures
Figure 1. 256-Pin CABGA and PBGA (Top View) ....................................................................................................................................................... 13
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 24
Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 25
Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 25
Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 26
Figure 6. Transmit Path Monitoring (COAX) ............................................................................................................................................................... 26
Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 27
Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 30
Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 30
Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 30
Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 43
Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 44
Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 46
Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 61
Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 62
Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 66
Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 66
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 72
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 73
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 73
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 74
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 75
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 75
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 76
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 81
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 82
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 82
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 83
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 84
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 84
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 85
Figure 32. DSX-1 Waveform Template ...................................................................................................................................................................... 100
Figure 33. T1/J1 Pulse Template Measurement Circuit ............................................................................................................................................ 100
Figure 34. E1 Waveform Template ............................................................................................................................................................................ 101
Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................. 101
Figure 36. G.772 Non-Intrusive Monitor .................................................................................................................................................................... 112
Figure 37. Hardware Reset When Powered-Up ........................................................................................................................................................ 115
Figure 38. Hardware Reset In Normal Operation ...................................................................................................................................................... 115
Figure 39. Read Operation In SPI Mode ................................................................................................................................................................... 116
Figure 40. Write Operation In SPI Mode .................................................................................................................................................................... 116
Figure 41. JTAG Architecture .................................................................................................................................................................................... 339
Figure 42. JTAG State Diagram ................................................................................................................................................................................ 345
Figure 43. I/O Timing in Mode ................................................................................................................................................................................... 348
Figure 44. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 352
Figure 45. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 353
Figure 46. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 355
Figure 47. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 356
Figure 48. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 357
List of Figures
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JANUARY 10, 2011