82P2288BB IDT, Integrated Device Technology Inc, 82P2288BB Datasheet - Page 66

• Manufacturer Part Number: 82P2288BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.15.2 E1 MODE
to Figure 13), which are Channel Associated Signalings (CAS). The
signaling codewords (ABCD) are clocked out on the RSIGn/
MRSIGA(MRSIGB) pins. They are in the lower nibble of the timeslot with
its corresponding data serializing on the RSDn/MRSDA(MRSDB) pins
(as shown in Figure 17).
sponding timeslot are extracted to the A,B,C,D bits in the Extracted
Signaling Data/Extract Enable register. The data in the A,B,C,D bits in
the register are the data to be output on the RSIGn/MRSIGA(MRSIGB)
pins. The bits corresponding to TS0 and TS16 output on the RSIGn/
MRSIGA(MRSIGB) pins are Don’t-Care.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received ABCD codewords of
the same timeslot are identical.
Functional Description
IDT82P2288
In Signaling Multi-Frame, the signaling bits are located in TS16 (refer
When the EXTRACT bit is set to ‘1’, the signaling bits in its corre-
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
MRSIGA(MRSIGB)
MRSDA(MRSDB)
MRSIGA(MRSIGB)
MRSDA(MRSDB)
RSIGn/
RSDn/
RSIGn/
RSDn/
1 2 3 4 5 6 7 8
1 2 3 4 5 6 78
Channel 24
TS31
ABCD
A B C D
1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS0
F-bit
Figure 16. Signaling Output In T1/J1 Mode
F
Figure 17. Signaling Output In E1 Mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Channel 1
TS1
ABCD
A B C D
1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
66
TS15
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Channel 2
frame synchronization, out of Signaling multi-frame synchronization or
slips occurs in the Elastic Store Buffer. It is also performed when the
FREEZE bit is set to ‘1’. The signaling freezing freezes the signaling
data in the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register as the previous valid value.
Extracted Signaling Data/Extract Enable register are changed, it is
captured by the corresponding COSI[X] bit (1 ≤ X ≤ 30). When the SIGE
bit is set to ‘1’, any one of the COSI[X] bits being ‘1’ will generate an
interrupt and will be reported by the INT pin.
the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
ABCD
Signaling freezing is performed automatically when it is out of Basic
Each time the extracted signaling bits in the A,B,C,D bits in the
The EXTRACT bit and the A,B,C,D bits are in the indirect registers of
A B C D
TS16
1 2 3 4 5 6 7 8
TS17
ABCD
Channel 24
A B C D
1 2 3 4 5 6 78 1 2 3 4 5 6 78
TS31
F-bit
ABCD
F
1 2 3 4 5 6 7 8
JANUARY 10, 2011
Channel 1
TS0
A B C D