82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 10

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1. 80-Pin TQFP (Top View) .............................................................................................................................................................................. 14
Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 24
Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 25
Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 25
Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 26
Figure 6. Transmit Path Monitoring(COAX) ................................................................................................................................................................ 26
Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 28
Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 30
Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 30
Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 30
Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 41
Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 42
Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 44
Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 55
Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 56
Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 60
Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 60
Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 65
Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 65
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 66
Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 67
Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 67
Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 68
Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 68
Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 72
Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 72
Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 73
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 74
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 74
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 75
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 75
Figure 32. DSX-1 Waveform Template ........................................................................................................................................................................ 90
Figure 33. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 90
Figure 34. E1 Waveform Template .............................................................................................................................................................................. 90
Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 90
Figure 36. Hardware Reset When Powered-Up ........................................................................................................................................................ 104
Figure 37. Hardware Reset In Normal Operation ...................................................................................................................................................... 104
Figure 38. Read Operation In SPI Mode ................................................................................................................................................................... 105
Figure 39. Write Operation In SPI Mode .................................................................................................................................................................... 105
Figure 40. JTAG Architecture .................................................................................................................................................................................... 347
Figure 41. JTAG State Diagram ................................................................................................................................................................................ 353
Figure 42. I/O Timing in Non-Multiplexed Mode ........................................................................................................................................................ 356
Figure 43. I/O Timing in Multiplexed Mode ................................................................................................................................................................ 357
Figure 44. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 362
Figure 45. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 363
Figure 46. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 364
Figure 47. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 365
Figure 48. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 366
List of Figures
10
August 20, 2009