82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 38

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
the previous one, the change of frame alignment event is generated.
This event is captured by the COFAI bit and is forwarded to the Perfor-
mance Monitor.
3.8.1.3
bits and Switch bits are all extracted to the RDL0, RDL1 & RDL2 regis-
ters respectively.
to ‘1’. Thus, the value in the RDL0, RDL1 & RDL2 registers are updated
if the received corresponding code is the same for 2 consecutive SLC-
96 frames. Whether de-bounced or not, a change indication will be set in
the SCCI bit, SCMI bit, SCAI bit and SCSI bit respectively if the corre-
sponding codes in the RDL0, RDL1 & RDL2 registers differ from the pre-
vious ones.
Functional Description
Table 16: Interrupt Source In T1/J1 Frame Processor
It is out of synchronization.
The first bit of each SF / ESF / T1 DM / SLC-96 frame is received.
The new-found F bit position differs from the previous one.
In SF / T1 DM / SLC-96 format, the F Bit Error occurs.
In ESF format, the Frame Alignment Bit Error occurs.
In ESF format, the CRC-6 Error occurs.
(This interrupt does not exist in other formats.)
In SF / T1 DM format, the Severely Ft Bit Error occurs.
In ESF format, the Severely Frame Alignment Bit Error occurs.
(This interrupt does not exist in SLC-96 format.)
In SLC-96 format, the Concentrator bits differ from the previous ones.
In SLC-96 format, the Maintenance bits differ from the previous ones.
In SLC-96 format, the Alarm bits differ from the previous ones.
In SLC-96 format, the Switch bits differ from the previous ones.
Once resynchronized, if the new-found F bit position differs from
In SLC-96 format, the Concentrator bits, Maintenance bits, Alarm
All these extractions will be set to de-bounce if the SCDEB bit is set
Overhead Extraction (T1 Mode SLC-96 Format Only)
Sources
38
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
SLC-96 synchronization state.
3.8.1.4
When there are conditions meeting the interrupt sources, the corre-
sponding Status bit will be asserted high. When there is a transition
(from ‘1’ to ‘0’ or from ‘0’ to ‘1’) on the Status bit, the corresponding Sta-
tus Interrupt Indication bit will be set to ‘1’ (If the Status bit does not
exist, the source will cause its Status Interrupt Indication bit to ‘1’
directly) and the Status Interrupt Indication bit will be cleared by writing
‘1’. A ‘1’ in the Status Interrupt Indication bit indicates an interrupt
occurred. The interrupt is reported by the INT pin if its Status Interrupt
Enable bit was set to ‘1’.
The value in the RDL0, RDL1 & RDL2 registers is held during out of
The interrupt sources in this block are summarized in Table 16.
Status Bit
Interrupt Summary
OOFV
-
-
-
-
-
-
-
-
-
Interrupt Indication Bit Interrupt Enable Bit
RMFBI
COFAI
SCMI
OOFI
SCCI
SCAI
SCSI
FERI
BEEI
SFEI
August 20, 2009
RMFBE
COFAE
OOFE
SCME
FERE
BEEE
SCCE
SCAE
SCSE
SFEE