82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 66

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
pin and the framing pulse on the RSFS pin to output the data on the
RSD pin are provided by the system side. The signaling bits on the
RSIG pin are per-channel aligned with the data on the RSD pin.
is clocked by the RSCK. The active edge of the RSCK used to sample
the pulse on the RSFS is determined by the FE bit. The active edge of
the RSCK used to update the data on the RSD and RSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
RSFS is ahead. The data rate of the system side is 1.544 Mb/s or 2.048
Mb/s. When it is 2.048 Mb/s, the RSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the RSCK is double
the data rate, there will be two active edges in one bit duration. In this
case, the EDGE bit determines the active edge to update the data on the
RSD and RSIG pins. The pulse on the RSFS pin is always sampled on
its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFS is selected by the FSINV bit. If the pulse on the
RSFS pin is not an integer multiple of 125 µs, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.3
be mapped to 2.048 Mb/s format first, the 3 kinds of schemes should be
selected by the MAP[1:0] bits. The mapping per G.802, per One Filler
Every Four CHs and per Continuous CHs are the same as the descrip-
tion in Chapter 3.17.1.2 Receive Clock Slave Mode.
put the data from the link. The data of the link is byte-interleaved output
on the multiplexed bus. When the data from the link is output on one
multiplexed bus, the position of the data is arranged by setting the chan-
nel offset.
pin and the framing pulse on the MRSFS pin are provided by the system
Functional Description
1.544
2.048
Mb/s
Mb/s
In the Receive Clock Slave mode, the timing signal on the RSCK
In the Receive Clock Slave mode, the data on the system interface
In the Receive Clock Slave mode, the RSFS asserts at a rate of
In the Receive Multiplexed mode, since the received data should
In the Receive Multiplexed mode, a multiplexed bus is used to out-
In the Receive Multiplexed mode, the timing signal on the MRSCK
filler
Receive Multiplexed Mode
TS0
the 8th bit
F
CH1
TS1
Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode
CH2
TS2
TS3
CH3
TS23
CH23
TS24
66
CH24
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
side . The signaling bits on the MRSIG pin are per-channel aligned with
the corresponding data on the MRSD pin.
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MRSFS is ahead. The MRSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MRSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to update the data
on the MRSD and MRSIG pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. If the pulse on the
MRSFS pin is not an integer multiple of 125 µs, this detection will be
indicated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.1.4
modes. The offset is between the framing pulse on RSFS/MRSFS pin
and the start of the corresponding frame output on the RSD/MRSD pin.
The signaling bits on the RSIG/MRSIG pin are always per-channel
aligned with the data on the RSD/MRSD pin.
TS25~TS31
In the Receive Multiplexed mode, the data on the system interface
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Bit offset and channel offset are both supported in all the operating
Figure 21 to Figure 24 show the base line without offset.
filler
F
CH1
Offset
filler
TS0
the 8th bit
CH2
TS1
TS2
CH24
August 20, 2009
F CH1
TS24