82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 75

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

BOFF[2:0] bits and the TSOFF[6:0] bits are not ‘0’ respectively.
the corresponding frame input on the TSD/MTSD pin will delay ‘N’ clock
cycles to the framing pulse on the TSFS/MTSFS pin. (Here ‘N’ is defined
by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and the TSOFF[6:0] bits
are set, the start of the corresponding frame input on the TSD/MTSD pin
will delay ‘8 x M’ clock cycles to the framing pulse on the TSFS/MTSFS
pin. (Here ‘M’ is defined by the TSOFF[6:0].)
BOFF[2:0] bits are set, the start of the corresponding frame input on the
IDT82P2281
The bit offset and channel offset are configured when the
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Master mode:
Transmit Clock Master mode:
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFS / MTSFS
TSCK / MTSCK
TSD / MTSD
TSFS / MTSFS
TSCK / MTSCK
TSD / MTSD
TSFS / MTSFS
TSCK / MTSCK
TSD / MTSD
TSFS / MTSFS
TSCK / MTSCK
TSD / MTSD
Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path
F-bit of CH1 (T1/J1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
FE = 0, DE = 1
FE = 1, DE = 0
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SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TSD/MTSD pin will delay ‘2 x N’ clock cycles to the framing pulse on the
TSFS/MTSFS pin. (Here ‘N’ is defined by the BOFF[2:0] bits.) When the
CMS bit is ‘1’ (i.e., in double clock mode) and the TSOFF[6:0] bits are
set, the start of the corresponding frame input on the TSD/MTSD pin will
delay ‘16 x M’ clock cycles to the framing pulse on the TSFS/MTSFS
pin. (Here ‘M’ is defined by the TSOFF[6:0].)
from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the
channel offset can be configured from 0 to 127 channels (0 & 127 are
included).
In Non-multiplexed mode, the channel offset can be configured
Bit 1 of CH1 (T1/J1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
August 20, 2009