82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 55

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
3.11
selected position and processes the data according to the selected
mode.
3.11.1
#2 & #3) are provided for HDLC extraction from the received data
stream. In T1/J1 mode SF & SLC-96 formats, two HDLC Receivers (#2
& #3) are provided for HDLC extraction. In E1 mode, three HDLC
Receivers (#1, #2 & #3) are provided for HDLC extraction. Except in T1/
J1 mode ESF & T1 DM formats, the HDLC channel of HDLC #1 is fixed
Table 29: Related Bit / Register In Chapter 3.11.1
3.11.2
Receiver selects the HDLC mode (per Q.921).
parts as shown in Figure 14. Each HDLC packet starts with a 7E (Hex)
opening flag and ends with the same flag. The closing flag may also
discarded, the data stream between the opening flag and the FCS is
divided into blocks. Each block (except the last block) has 32 bytes. The
Functional Description
BITEN[7:0]
The HDLC Receiver extracts the HDLC data stream from the
In T1/J1 mode ESF & T1 DM formats, three HDLC Receivers (#1,
Setting the RHDLCM bit to ‘0’ (default) in the corresponding HDLC
The structure of a standard HDLC packet consists of the following
After the stuffed zero (the zero following five consecutive ’One’s) is
- The data between the opening flag and the closing flag is less
RDLEN3
RDLEN2
RDLEN1
'01111110'
TS[4:0]
EVEN
one byte
ODD
Bit
Flag
HDLC RECEIVER
HDLC CHANNEL CONFIGURATION
HDLC MODE
RHDLC1 Assignment (E1 only) / RHDLC2 Assignment /
RHDLC1 Bit Select (E1 only) / RHDLC2 Bit Select /
two bytes
FCS
RHDLC Enable Control
RHDLC3 Assignment
RHDLC3 Bit Select
Register
Figure 14. Standard HDLC Packet
Information
n bytes
b7
55
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
in the DL bit (in ESF format) and D bit in CH24 (in T1 DM format) respec-
tively (refer to Table 13 & Table 14), the other HDLC channels are con-
figured as follows:
odd frames;
assigned frame;
timeslot.
the corresponding RDLEN bit is set to ‘1’.
serve as the opening flag of the next HDLC packet. Following the open-
ing flag, two-byte address is compared if the address comparison mode
is selected. Before the closing flag, two bytes of CRC-CCITT frame
check sequences (FCS) are provided to check all the HDLC packet
(excluding the opening flag and closing flag).
block will be pushed into a FIFO with one-byte overhead ahead until any
of the following invalid packet conditions occurs:
than 5 bytes (including the FCS, excluding the flags);
1. Set the EVEN bit and/or the ODD bit to select the even and/or
2. Set the TS[4:0] bits to define the channel/timeslot of the
3. Set the BITEN[7:0] bits to select the bits of the assigned channel/
Then all the functions of the HDLC Receiver will be enabled only if
- A packet with error FCS;
one byte
Control
one byte
low byte
address
08C (E1 only) / 08D / 08E
b0
08F (E1 only) / 090 / 091
(optional)
Address
b7
Address (Hex)
high byte
one byte
address
08B
'01111110'
one byte
Flag
August 20, 2009
C/R
b0