82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 62

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
3.16
or the received data stream can be extracted to the PRBS Generator/
Detector for test in this block.
PCCE bit must be set to ‘1’.
the RSD/MRSD pins on a per-channel/per-TS basis or on a global basis
(the methods are arranged from the highest to the lowest in priority):
received data will be extracted to the PRBS Generator/Detector. The
received data can be extracted in unframed mode, in 8-bit-based mode
or in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the received data stream is extracted and the
per-channel/per-TS configuration in the TEST bit is ignored. In 8-bit-
based mode or in 7-bit-based mode, the received data will only be
extracted on the channel/timeslot configured by the TEST bit. Refer to
Chapter 3.27.1 PRBS Generator / Detector for details.
timeslots will be replaced by the data trunk code set in the DTRK[7:0]
bits, or the milliwatt pattern defined in the Table 36 and Table 37. When
the GSUBST[2:0] bits are set to ‘000’, these replacements will be per-
formed on a per-channel/per-TS basis by setting the SUBST[2:0] bits in
the corresponding channel/timeslot.
fixed to the value set in the POL bit. This function is only supported in
the SF, ESF and SLC-96 formats in T1/J1 mode.
setting the SINV, OINV, EINV bits.
received data will be replaced by the test pattern generated from the
PRBS Generator/Detector. The received data can be replaced in
unframed mode, in 8-bit-based mode or in 7-bit-based mode. This selec-
tion is made by the PRBSMODE[1:0] bits. In unframed mode, all the
received data stream is replaced and the per-channel/per-TS configura-
tion in the TEST bit is ignored. In 8-bit-based mode or in 7-bit-based
mode, the received data will only be replaced on the channel/timeslot
configured by the TEST bit. Refer to Chapter 3.27.1 PRBS Generator /
Detector for details.
Functional Description
Different test patterns can be inserted in the received data stream
To enable all the functions in the Receive Payload Control, the
The following methods can be executed on the data to be output on
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
- Selected by the GSUBST[2:0] bits, the data of all channels/
- When the SIGFIX bit is set to ‘1’, the signaling bits (ABCD) will be
- Invert the most significant bit, the even bits and/or the odd bits by
- When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
RECEIVE PAYLOAD CONTROL
62
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
output on the RSIG/MRSIG pins on a per-channel/per-TS basis or on a
global basis (the methods are arranged from the highest to the lowest in
priority):
upper 2-bit positions of the lower nibble of each channel or in the lower
nibble of each channel. The other bits of the channel are Don’t Care
conditions. This function is only supported in T1/J1 mode ESF/SLC-96
format.
cuted. The signaling snapshot means that the signaling bits of the first
basic frame are locked and output as the signaling bits of the current
whole multi-frame. This function is not supported in T1 DM format.
channels/timeslots will be replaced by the signaling trunk conditioning
code in the A,B,C,D bits. When the GSTRKEN bit is ‘0’, the replacement
will be performed on a per-channel/per-TS basis by setting the STRKEN
bit in the corresponding channel/timeslot.
by specifying the address in the ADDRESS[6:0] bits. Whether the data is
Table 37: µ-Law Digital Milliwatt Pattern
Table 36: A-Law Digital Milliwatt Pattern
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
The following methods can be executed on the signaling bits to be
- Selected by the ABXX bit, the signaling bits can be valid in the
- Enabled by the SIGSNAP bit, the signaling snapshot will be exe-
- Enabled by the GSTRKEN bit, the signaling bits (ABCD) of all
The indirect registers of the Receive Payload Control are accessed
Bit 0
Bit 0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
Bit 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 2
Bit 2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Bit 3
Bit 3
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Bit 4
Bit 4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 5
Bit 5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
August 20, 2009
Bit 6
Bit 6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 7
Bit 7
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0