82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 79

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

3.20
3.20.1
3.20.1.1
Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer
(DM) or Switch Line Carrier - 96 (SLC-96) format.
3.20.1.1.1
‘10001101110X’ for J1) will replace the F-bit of each frame if the FDIS bit
is set to ‘0’. The F-bit of the 12th frame in J1 mode should be ‘0’ unless
Yellow alarm signal is transmitted.
Table 12) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 12) will be inverted if the FsINV bit is set.
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The pattern
and the position of the Yellow alarm is different in T1 and J1 modes:
each channel;
position.
3.20.1.1.2
Frame (4n) (0<n<7) if the FDIS bit is set to ‘0’.
for its position) will be inverted if the FsINV bit is set.
lated 6-bit CRC of the previous ESF frame will be inserted in the current
CRC-bit positions in every 4th frame starting with Frame 2 (refer to
Table 13) of the current ESF frame.
the CRCINV bit is set.
replaced with the Yellow alarm signal, the Bit-Oriented Code (refer to
Chapter 3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only)), the
Automatic Performance Report Message (refer to Chapter 3.20.3 Auto-
matic Performance Report Message (T1/J1 Only)), the HDLC data (refer
to Chapter 3.20.2 HDLC Transmitter) or the idle code (‘FFFF’ for T1 /
‘FF7E’ for J1). The latter four kinds of replacements are enabled only if
the FDLBYP bit is set to ‘0’. When all of the five kinds of replacements
are enabled, the priority from highest to lowest is: Yellow alarm signal,
IDT82P2281
In T1/J1 mode, the data to be transmitted can be generated as
The SF is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘100011011100’ for T1 /
When the FDIS bit is ‘0’, one Ft bit (the F-bit in odd frame, refer to
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
The Yellow alarm signal will be manually inserted in the data
- In T1 mode, the Yellow alarm signal is logic 0 on the 2nd bit of
- In J1 mode, the Yellow alarm signal is logic 1 on the 12th F-bit
The ESF is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘001011’) will replace the F-bit in
When the FDIS bit is ‘0’, one Frame Alignment bit (refer to Table 13
When the FDIS bit and the CRCBYP bit are both ‘0’s, the calcu-
When the FDIS bit is ‘0’, one 6-bit CRC pattern will be inverted if
When the FDIS bit is ‘0’, the DL bit (refer to Table 13) can be
FRAME GENERATOR
GENERATION
T1 / J1 Mode
Super Frame (SF) Format
Extended Super Frame (ESF) Format
79
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit-Oriented Code, Automatic Performance Report Message, HDLC
data and idle code.
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is transmitted in the DL bit position. Its pattern is ‘FF00’ in
T1 mode or ‘FFFF’ in J1 mode.
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
3.20.1.1.3
bit of each frame if the FDIS bit is set to ‘0’.
Table 14) will be inverted if the FtINV bit is set; one Fs bit (the F-bit in
even frame, refer to Table 14) will be inverted if the FsINV bit is set.
pattern can be inserted into the bit right after each F-bit. The content of
the mimic pattern is the same as the F-bit. The mimic pattern insertion is
for diagnostic purpose.
the Bit 8 & 5~1 of each Channel 24 (refer to Table 14).
DDSINV bit is set.
HDLC data when the FDIS bit and the FDLBYP bit are both ‘0’s. (Refer
to Chapter 3.20.2 HDLC Transmitter for details).
stream to be transmitted when the XYEL bit is set, or the Yellow alarm
signal will be inserted automatically by setting the AUTOYELLOW bit
when Red alarm is declared in the received data stream. The Yellow
alarm signal is ‘0’ transmitted in the ‘Y’ bit in Bit 6 of each Channel 24.
The ‘Y’ bit should be ‘1’ when there is no Yellow alarm signal to be trans-
mitted.
3.20.1.1.4
Spoiler Bit and all the other Ft bits (the F-bit in odd frame) will replace
their F-bit (refer to Table 15 for their values and positions) if the FDIS bit
is set to ‘0’.
if the FsINV bit is set; one Ft bit will be inverted if the FtINV bit is set.
in the XDL0, XDL1 & XDL2 registers will replace the Concentrator (C)
bits, the Maintenance (M) bits, the Alarm (A) bits and the Switch (S) bits
respectively (refer to Table 15).
pattern can be inserted into the bit right after each F-bit. The content of
The Yellow alarm signal will be manually inserted in the data
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
The T1 DM is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘100011011100’) will replace the F-
When the FDIS bit is ‘0’, one Ft bit (the F-bit in odd frame, refer to
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
When the FDIS bit is ‘0’, the DDS pattern (‘0XX11101’) will replace
When the FDIS bit is ‘0’, one 6-bit DDS pattern will be inverted if the
The ‘D’ bit in Bit 7 of each Channel 24 can be replaced with the
The Yellow alarm signal will be manually inserted in the data
The SLC-96 is generated when the FDIS bit is ‘0’.
The Frame Alignment Pattern (‘001000110111001000110111’), the
When the FDIS bit is ‘0’, one Synchronization Fs bit will be inverted
When the FDIS bit and the FDLBYP bit are both ‘0’s, the contents
When the FDIS bit is ‘0’, configured by the MIMICEN bit, the mimic
T1 Digital Multiplexer (DM) Format (T1 only)
Switch Line Carrier - 96 (SLC-96) Format (T1 only)
August 20, 2009