82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 89

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

3.23
This selection is made by the TJA_E bit.
Figure 7.
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the TJA_DP[1:0]
bits. Accordingly, the constant delay produced by the Jitter Attenuator is
16 bits, 32 bits or 64 bits. The 128-bit FIFO is used when large jitter tol-
erance is expected, and the 32-bit FIFO is used in delay sensitive appli-
cations.
data stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter which fre-
quency is lower than the CF passes through the DPLL without any atten-
uation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or 1.26
Hz, as selected by the TJA_BW bit. In E1 applications, the CF of the
DPLL can be 6.77 Hz or 0.87 Hz, as selected by the TJA_BW bit. The
lower the CF is, the longer time is needed to achieve synchronization.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
TJA_IS bit. When the TJA_IS bit is ‘1’, an interrupt will be reported on
the INT pin if enabled by the TJA_IE bit.
enabled by setting the TJA_LIMT bit. When the JA-Limit function is
enabled, the speed of the outgoing data will be adjusted automatically if
the FIFO is close to its full or emptiness. The criteria of speed adjust-
ment start are listed in Table 6. Though the LA-Limit function can reduce
the possibility of FIFO overflow and underflow, the quality of jitter attenu-
ation is deteriorated.
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the TJITT[6:0]
bits. When the TJITT_TEST bit is ‘0’, the current interval between the
read and write pointer of the FIFO will be written into the TJITT[6:0] bits.
When the TJITT_TEST bit is ‘1’, the current interval is compared with
the old one in the TJITT[6:0] bits and the larger one will be indicated by
the TJITT[6:0] bits.
I.431, G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/
13, AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.11 Jitter
Transfer for details.
IDT82P2281
The Transmit Jitter Attenuator can be chosen to be used or not.
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
The FIFO is used as a pool to buffer the jittered input data, then the
The DPLL is used to generate a de-jittered clock to clock out the
If the incoming data moves faster than the outgoing data, the FIFO
To avoid overflowing or underflowing, the JA-Limit function can be
Selected by the TJITT_TEST bit, the real time interval between the
The performance of Receive Jitter Attenuator meets the ITUT
TRANSMIT JITTER ATTENUATOR
89
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 59: Related Bit / Register In Chapter 3.23
TJA_DP[1:0]
TJITT_TEST
TJA_LIMT
TJITT[6:0]
TJA_BW
TJA_IS
TJA_IE
TJA_E
Bit
Transmit Jitter Attenuation Configuration
Transmit Jitter Measure Value Indication
Interrupt Enable Control 1
Interrupt Status 1
Register
August 20, 2009
Address (Hex)
021
03B
034
038