82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 71

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

3.18
the device. The timing clocks and framing pulses can be provided by the
system backplane or obtained from the processed data. The Transmit
System Interface supports various configurations to meet various
requirements in different applications.
3.18.1
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSD pin is used to input the data at the bit rate of 1.544 Mb/s or
2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed Mode, the
data is byte-interleaved from one high speed data stream and inputs on
the MTSD pin at the bit rate of 8.192 Mb/s. The demultiplexed data input
to the link is 2.048 Mb/s on the system side and converted into 1.544
Mb/s format to the device.
Table 42: Operating Modes Selection In T1/J1 Transmit Path
3.18.1.1
pin and framing pulse on the TSFS pin are used to input the data on the
TSD pin. The signaling bits on the TSIG pin are per-channel aligned with
the data on the TSD pin.
face is clocked by the TSCK. The active edge of the TSCK used to
update the pulse on the TSFS is determined by the FE bit. The active
edge of the TSCK used to sample the data on the TSD and TSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFS is ahead.
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFS is selected by the FSINV bit.
IDT82P2281
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Transmit Multiplexed mode.
TMUX TMODE
0
1
The Transmit System Interface determines how to input the data to
In T1/J1 mode, the Transmit System Interface can be set in Non-
In the Transmit Clock Master mode, the timing signal on the TSCK
In the Transmit Clock Master mode, the data on the system inter-
In the Transmit Clock Master mode, the TSFS can indicate each F-
TRANSMIT SYSTEM INTERFACE
X
0
1
T1/J1 MODE
Transmit Clock Master Mode
G56K, GAP /
not all 0s
FBITGAP
00 / 0
X
X
1
MAP[1:0]
00
01
10
01
10
11
11
X
2
Transmit Clock Master Full T1/J1
Transmit Clock Master Fractional T1/J1
Transmit Clock Slave - T1/J1 Rate
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
Operating Mode
71
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TSFSn, however in Transmit Clock Slave mode, TSCKn & TSFSn are
input the device from outside.
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCK, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s or 8.192 Mb/s.
If the backplane data rate is 2.048 Mb/s or 8.192 Mb/s, the Transmit
System Interface is in T1/J1 mode E1 rate and the data to be transmitted
will be mapped to 1.544 Mb/s i device per 3 kinds of schemes.
various operating modes and the pins’ direction of the transmit system
interface in different operating modes.
mit Clock Master Full T1/J1 mode and Transmit Clock Master Fractional
T1/J1 mode.
3.18.1.1.1
Master mode, the special feature in this mode is that the TSCK is a stan-
dard 1.544 MHz clock, and the data in the F-bit and all 24 channels in a
standard T1/J1 frame are clocked in by the TSCK.
3.18.1.1.2
Master mode, the special feature in this mode is that the TSCK is a
gapped 1.544 MHz clock (no clock signal during the selected channel).
The TSCK is also gapped during the channels or the Bit 8 duration by
In Transmit Clock Master mode, the device output TSCKn and
In the Transmit Clock Master mode, if TSCK outputs pulses during
In the Transmit Clock Slave mode, the backplane data rate may be
Table 42 summarizes how to set the transmit system interface into
The Transmit Clock Master mode includes two sub-modes: Trans-
Besides all the common functions described in the Transmit Clock
Besides all the common functions described in the Transmit Clock
The TSCK is gapped during the F-bit if the FBITGAP bit is set to ‘1’.
Transmit Clock Master Full T1/J1 Mode
Transmit Clock Master Fractional T1/J1 Mode
TSD, TSIG, TSCK, TSFS
MTSCK, MTSFS, MTSD,
Transmit System Interface Pin
TSD, TSIG
MTSIG
Input
August 20, 2009
TSCK, TSFS
Output
X
X