82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 101

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

3.27.2
2, Remote Loopback and Analog Loopback are all supported in the
IDT82P2281. Their routes are shown in the Functional Block Diagram.
3.27.2.1
System Interface and the Transmit System Interface are in different
Non-multiplexed operating modes (one in Clock Master mode and the
other in Clock Slave mode). However, in T1/J1 mode, when either the
receive path or the transmit path is in T1/J1 mode E1 rate, the System
Loopback is not supported.
be divided into System Remote Loopback and System Local Loopback.
When the data and signaling bits from the transmit path are looped to
the receive path, it is System Remote Loopback. When the data and sig-
naling bits from the receive path are looped to the transmit path, it is
System Local Loopback.
3.27.2.1.1
mented. The data and signaling bits to be transmitted on the TSD and
TSIG pins are internally looped to the RSD and RSIG pins. When the
receive path is in Receive Clock Master mode and the transmit path is in
Transmit Clock Slave mode, the clock signal and the framing pulse from
the system side on the TSCK and TSFS pins are looped to the RSCK
and RSFS pins respectively. When the transmit path is in Transmit Clock
Master mode and the receive path is in Receive Clock Slave mode, the
clock signal and the framing pulse from the system side on the RSCK
and RSFS pins are looped to the TSCK and TSFS pins respectively.
ted is still output to the line side, while the data stream received from the
line side is replaced by the System Remote Loopback data.
3.27.2.1.2
mented. The received data and signaling bits to be output on the RSD
and RSIG pins are internally looped to the TSD and TSIG pins. When
the receive path is in Receive Clock Master mode and the transmit path
is in Transmit Clock Slave mode, the recovered clock signal and framing
pulse on the RSCK and RSFS pins are looped to the TSCK and TSFS
pins respectively. When the transmit path is in Transmit Clock Master
mode and the receive path is in Receive Clock Slave mode, the TSCK
and TSFS pins are looped to the RSCK and RSFS pins respectively.
the line side is still output to the system through the RSD and RSIG pins,
while the data stream to be transmitted through the TSD and TSIG pins
are replaced by the System Local Loopback data.
IDT82P2281
System Loopback, Payload Loopback, Local Digital Loopback 1 &
The System Loopback can only be implemented when the Receive
Distinguished by the loopback direction, the System Loopback can
Enabled by the SRLP bit, the System Remote Loopback is imple-
In System Remote Loopback mode, the data stream to be transmit-
Enabled by the SLLP bit, the System Local Loopback is imple-
In System Local Loopback mode, the data stream received from
LOOPBACK
System Loopback
System Remote Loopback
System Local Loopback
101
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
August 20, 2009