82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 48

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
3.9
3.9.1
formance monitoring. For different framing format, the counters are used
differently. The overflow of each counter is reflected by an Overflow Indi-
cation Bit, and can trigger an interrupt if the corresponding Overflow
Interrupt Enable Bit is set. This is shown in Table 22.
Table 22: Monitored Events In T1/J1 Mode
Functional Description
(T1 only)
(T1 only)
Format
SLC-96
T1 DM
ESF
SF
Several internal counters are used to count different events for per-
The internal counters can be updated in two ways:
PERFORMANCE MONITOR
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
F Bit Error
The new-found F bit position differs from the previous one
Out of SF synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
Frame Alignment Bit Error
CRC-6 Error
The new-found F bit position differs from the previous one
Out of ESF synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
F Bit Error
DDS Pattern Error
The new-found F bit position differs from the previous one
Out of T1 DM synchronization
PRGD Bit Error
Bipolar Violation (BPV) Error (in AMI decoding) or B8ZS Code
Violation (CV) Error (in B8ZS decoding)
F Bit Error
The new-found F bit position differs from the previous one
Out of SLC-96 synchronization
PRGD Bit Error
T1/J1 MODE
Event
PRGD[15:0]
PRGD[15:0]
PRGD[15:0]
PRGD[15:0]
48
CRCE[9:0]
COFA[2:0]
COFA[2:0]
DDSE[9:0]
COFA[2:0]
COFA[2:0]
LCV[15:0]
FER[11:0]
LCV[15:0]
FER[11:0]
LCV[15:0]
FER[11:0]
LCV[15:0]
FER[11:0]
OOF[4:0]
OOF[4:0]
OOF[4:0]
OOF[4:0]
Counter
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
indirect registers every one second automatically if the AUTOUPD bit is
‘1’;
indirect registers when there is a transition from ‘0’ to ‘1’ on the UPDAT
bit, no matter whether the AUTOUPD bit is ‘1’ or ‘0’.
start a new round of counting. No error event is lost during the update.
ADDR[3:0] bits select the specific PMON indirect register. Data read
from the indirect register is held in the DAT[7:0] bits.
1. Auto-Update: Content in the internal counters is transferred to
2. Manual-Update: Content in the internal counters is transferred to
All the internal counters will be resetted after the update and will
The indirect registers are addressed by the ADDR[3:0] bits. The
Overflow Interrupt Indication Bit Overflow Interrupt Enable Bit
PRGDOVI
PRGDOVI
PRGDOVI
PRGDOVI
COFAOVI
COFAOVI
COFAOVI
COFAOVI
OOFOVI
CRCOVI
OOFOVI
DDSOVI
OOFOVI
OOFOVI
LCVOVI
FEROVI
LCVOVI
FEROVI
LCVOVI
FEROVI
LCVOVI
FEROVI
PRGDOVE
PRGDOVE
PRGDOVE
PRGDOVE
COFAOVE
COFAOVE
COFAOVE
COFAOVE
OOFOVE
CRCOVE
OOFOVE
OOFOVE
OOFOVE
FEROVE
FEROVE
FEROVE
DDSOVE
FEROVE
August 20, 2009
LCVOVE
LCVOVE
LCVOVE
LCVOVE