82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 70

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
the pulse on the RSFS is determined by the FE bit. The active edge of
the RSCK used to update the data on the RSD and RSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
RSFS is ahead. The speed of the RSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the RSCK is double
the data rate, there will be two active edges in one bit duration. In this
case, the EDGE bit determines the active edge to update the data on the
RSD and RSIG pins. The pulse on the RSFS pin is always sampled on
its first active edge.
integer multiple of 125 µ s to indicate the start of a frame. The active
polarity of the RSFS is selected by the FSINV bit. If the pulse on the
RSFS pin is not an integer multiple of 125 µ s, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.3
output the data from the link. The data of the link is byte-interleaved out-
put on the multiplexed bus. When the data from the link is output on one
multiplexed bus, the position of the data is arranged by setting the
timeslot offset.
pin and the framing pulse on the MRSFS pin are provided by the system
side. The signaling bits on the MRSIG pin are per-timeslot aligned with
the corresponding data on the MRSD pin.
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MRSFS is ahead. The MRSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MRSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to update the data
on the MRSD and MRSIG pins. The pulse on the MRSFS pin is always
sampled on its first active edge.
integer multiple of 125 µ s to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. If the pulse on the
MRSFS pin is not an integer multiple of 125 µ s, this detection will be
indicated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt
will be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFS/MRSFS
pin and the start of the corresponding frame output on the RSD/MRSD
pin. The signaling bits on the RSIG/MRSIG pin are always per-timeslot
aligned with the data on the RSD/MRSD pin.
Functional Description
In the Receive Clock Slave mode, the RSFS asserts at a rate of
In the Receive Multiplexed mode, one multiplexed bus is used to
In the Receive Multiplexed mode, the timing signal on the MRSCK
In the Receive Multiplexed mode, the data on the system interface
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Except that in the Receive Master mode, when the OHD bit, the
Receive Multiplexed Mode
Offset
70
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
different operating modes and the configuration of the offset.
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
3.17.2.5
configured by the TRI bit to be in high impedance state or to output the
processed data stream.
Table 41: Related Bit / Register In Chapter 3.17
Note:
* ID means Indirect Register in the Receive Payload Control function block.
ALTIFS (T1/J1 only)
FBITGAP (T1/J1
MAP[1:0] (T1/J1
SMFS (E1 only)
OHD (E1 only)
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured
The output on the RSD/MRSD and the RSIG/MRSIG pins can be
TSOFF[6:0]
BOFF[2:0]
RCOFAE
RMODE
RCOFAI
RMUX
CMFS
FSINV
EDGE
PCCE
G56K
CMS
only)
GAP
only)
TRI
Bit
FE
DE
Output On RSD/MRSD & RSIG/MRSIG
Backplane Global Configuration
ID * - Channel Control (for T1/
J1) / Timeslot Control (for E1)
RTSFS Change Indication
RTSFS Interrupt Control
RPLC Control Enable
RBIF Frame Pulse
RBIF Operation
RBIT TS Offset
RBIF Bit Offset
RBIF Mode
Register
T1/J1) / 00~1F (for E1)
RPLC ID - 01~18 (for
August 20, 2009
Address (Hex)
04BH
0D1
04A
04C
010
047
046
048
049