82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 347

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

IDT82P2281
6
ACCESS PORT
as described in the IEEE 1149.1 standards.
registers plus a Test Access Port (TAP) controller. Control of the TAP is
achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
IEEE STD 1149.1 JTAG Test Access Port
The IDT82P2281 supports the digital Boundary Scan Specification
The boundary scan architecture consists of data and instruction
IEEE STD 1149.1 JTAG TEST
TRST
TMS
TCK
TDI
(Test Access Port)
Controller
TAP
DIR (Device Identification Register)
BSR (Boundary Scan Register)
IR (Instruction Register)
BR (Bypass Register)
Figure 40. JTAG Architecture
Control<6:0>
347
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
Register), DIR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure - 40 for architecture.
The JTAG boundary scan registers include BSR (Boundary Scan
Output Enable
Select
MUX
August 20, 2009
TDO