82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 105

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

4.4
registers in the device. The interface consists of Serial Peripheral Inter-
face (SPI) and parallel microprocessor interface.
Instruction
Operation
IDT82P2281
Instruction
SCLK
SCLK
SDO
SDO
SDI
SDI
CS
CS
The microprocessor interface provides access to read and write the
MICROPROCESSOR INTERFACE
0
0
X
X
1
1
X
X
2
2
X A11 A10 A9
X A11 A10
3
3
4
4
High Impedance
High Impedance
5
5
A9
Figure 39. Write Operation In SPI Mode
Figure 38. Read Operation In SPI Mode
6
6
A8
A8
7
7
Register Address
Register Address
A7 A6 A5 A4 A3 A2 A1
A7 A6 A5 A4 A3 A2 A1
8
8
9
9
10
10
105
11 12 13 14 15 16 17 18 19 20 21 22 23
11 12 13 14 15 16 17 18 19 20 21 22 23
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4.4.1
set in SPI mode.
with the microprocessor. A falling transition on CS pin indicates the start
of a read/write operation, and a rising transition indicates the end of the
operation. After the CS pin is set to low, two bytes include instruction
and address bytes on the SDI pin is input to the device on the rising
edge of the SCLK pin. First byte consists of one instruction bit at MSB
and three address bits at LSB, the second byte is low 8 address bits. If
the MSB is ‘1’, it is read operation. If the MSB is ‘0’, it is write operation.
If the device is in read operation, the data read from the specified regis-
ter is output on the SDO pin on the falling edge of the SCLK (refer to
Figure 38). If the device is in write operation, the data written to the
specified register is input on the SDI pin following the address byte (refer
to Figure 39).
Pull the SPIEN pin to high, and the microprocessor interface will be
In this mode, only the CS , SCLK, SDI and SDO pins are interfaced
SPI MODE
A0
A0
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1
Data Byte
Don't Care
August 20, 2009
D0
D0