82P2281PFG IDT, Integrated Device Technology Inc, 82P2281PFG Datasheet - Page 88

• Manufacturer Part Number: 82P2281PFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2281PFG

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

3.21
timing is different from the line side timing in Transmit Slave mode.
source of the transmit clock can be selected in the recovered clock from
the line side, the processed clock from the backplane or the master
clock generated by the clock generator.
ically. The source of the transmit clock can be selected between the
recovered clock from the line side and the master clock generated by
the internal clock generator (1.544 MHz in T1/J1 mode or 2.048 MHz in
E1 mode). The selection is made by the XTS bit.
ing is 2.048 MHz from backplane and the line timing is 1.544 MHz from
the internal clock generator, the Transmit Buffer is selected automati-
cally to absorb high frequency mapping jitter due to the E1 to T1/J1
mapping scheme. In this case, 1.544 MHz must be locked to 2.048 MHz
by PLL of the internal clock generator. The XTS bit in the Transmit Tim-
ing Option register does not take effect.
is bypassed and the source of the transmit clock selection are selected
by the XTS bit. When the XTS bit is set to ‘1’, line side timing is from
internal clock generator, but backplane timing is from backplane, so the
Transmit Buffer is selected to accommodate the different clocks. If these
two clocks are not locked, an internal slip will occur in the Transmit
Buffer. The source of the transmit clock is from the master clock gener-
ated by the internal clock generator (1.544 MHz in T1/J1 mode or 2.048
MHz in E1 mode). When the XTS bit is set to ‘0’, the line side timing is
also from the backplane timing, so the Transmit Buffer is bypassed. The
source of the transmit clock is from the processed clock from the back-
plane.
bypassed and the source of the transmit clock selection are the same as
that described in other Transmit Clock Slave modes.
be set to ‘0’ to bypass the Transmit Buffer (The Transmit Buffer is
selected automatically in T1/J1 mode E1 rate).
IDT82P2281
Table 57: Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 &
Chapter 3.21
Transmit Buffer can be used in the circumstances that backplane
The function of timing option is also integrated in this block. The
In Transmit Master mode, the Transmit Buffer is bypassed automat-
In Transmit Clock Slave T1/J1 mode E1 rate, for the backplane tim-
In other Transmit Clock Slave modes, whether the Transmit Buffer
In Transmit Multiplexed mode, whether the Transmit Buffer is
In most applications of Transmit Clock Slave mode, the XTS bit can
COFAEN
TXDIS
TAIS
XTS
Bit
TRANSMIT BUFFER
Transmit Timing Option
FGEN Maintenance 1
Register
Address (Hex)
06C
070
88
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.22
3.22.1
3.22.1.1
can be selected by the T_MD bit.
3.22.1.2
be selected by the T_MD bit.
3.22.2
be transmitted by a transition from ‘0’ to ‘1’ on the BPV_INS bit.
3.22.3
inserted automatically to the data stream to be transmitted by setting the
ATAO bit.
Table 58: Related Bit / Register In Chapter 3.22
BPV_INS
T_MD
ATAO
In T1/J1 mode, the B8ZS line code rule or the AMI line code rule
In E1 mode, the HDB3 line code rule or the AMI line code rule can
For test purpose, a BPV error can be inserted to the data stream to
When the LOS is detected in the receive path, all ‘One’s will be
Bit
ENCODER
LINE CODE RULE
BPV ERROR INSERTION
ALL ‘ONE’S INSERTION
T1/J1 Mode
E1 Mode
Maintenance Function Control 2
Maintenance Function Control 1
Transmit Configuration 0
Register
August 20, 2009
Address (Hex)
02C
022
031