RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet
RG82845 S L5YQ
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... R ® Intel 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR Datasheet January 2002 Document Number: 290725-002 ...
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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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... Intel 82845 MCH for SDR Datasheet System Bus Interface ............................................................................15 System Bus Error Checking ..................................................................15 System Memory Interface .....................................................................16 AGP Interface........................................................................................16 Hub Interface.........................................................................................17 ® Intel MCH Clocking ..............................................................................17 System Interrupts ..................................................................................18 Powerdown Flow ...................................................................................18 AGP Addressing Signals .......................................................................24 AGP Flow Control Signals .....................................................................25 AGP Status Signals ...............................................................................25 AGP Strobes Signals.............................................................................26 AGP/PCI Signals ...
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... RID1—Revision Identification Register (Device 1)................................84 SUBC1—Sub-Class Code Register (Device 1).....................................84 BCC1—Base Class Code Register (Device 1)......................................84 MLT1—Master Latency Timer Register (Device 1) ...............................85 HDR1—Header Type Register (Device 1) ............................................85 PBUSN1—Primary Bus Number Register (Device 1) ...........................85 ® Intel 82845 MCH for SDR Datasheet R ...
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... System Memory Interface ...................................................................................109 5.2.1 5.2.2 5.2.3 5.2.4 ® Intel 82845 MCH for SDR Datasheet SBUSN1—Secondary Bus Number Register (Device 1) ......................86 SUBUSN1—Subordinate Bus Number Register (Device 1)..................86 SMLT1—Secondary Master Latency Timer Register (Device 1) .........87 IOBASE1—I/O Base Address Register (Device 1) ...............................88 IOLIMIT1— ...
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... XOR Chains ........................................................................................................138 6 AGP Target Operations.......................................................................112 AGP Transaction Ordering ..................................................................114 AGP Signal Levels...............................................................................114 4x AGP Protocol..................................................................................114 Fast Writes ..........................................................................................114 AGP FRAME# Transactions on AGP ..................................................115 Processor Power State Control ...........................................................117 Sleep State Control .............................................................................118 ® Intel 82845 MCH for SDR Datasheet R ...
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... Table 12. Supported DIMM Configurations .....................................................................109 Table 13. Data Bytes on DIMM Used for Programming DRAM Registers ......................110 Table 14. Address Translation and Decoding .................................................................111 Table 15. AGP Commands Supported by the Intel an AGP Target .................................................................................................113 Table 16. Data Rate Control Bits .....................................................................................115 Table 17. PCI Commands Supported by the Intel as a FRAME# Target) ...
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... DWTC—DRAM Write Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device 1. DRTC—DRAM Read Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device 1. 8 Description ® Intel 82845 MCH for SDR Datasheet R Date September 2001 January 2002 ...
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... GB Maximum using 512 Mb technology Supports simultaneous open pages Maximum memory bandwidth of 1.067 GB/s with PC133 ! Hub Interface to Intel 266 MB/s point-to-point hub interface to ICH2 66 MHz base clock MSI interrupt messages, power management state change, SMI, SCI and SERR error indication ® ...
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... Intel 82801BA AC'97 2.1 I/O Controller Hub (ICH2) GPIO FW H Flash BIOS 845 Chipset System Memory SDRAM Interface SDRAM PCI Slots PCI Bus PCI Agent Keyboard, LPC I/F Super I/O Mouse, FD, PP, SP, IR sys_blk ® Intel 82845 MCH for SDR Datasheet R ...
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... Memory Controller Hub (MCH) is designed for use with the Intel processor in the 478-pin package. The Intel 82845 Memory Controller Hub (MCH) for the host bridge and the Intel 82801BA I/O Controller Hub (ICH2) for the I/O subsystem. The MCH provides the processor interface, system memory interface, AGP interface, and hub interface in an 845 chipset desktop platform ...
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... Quadword: 8 bytes = 4 words Double Quadword. 16 bytes or 8 words. This is sometimes referred Superword (SW or SWord), and is also referred “Cache Line”. 1024 bytes 1, 048,576 bits = 128 KB 1,048,576 bytes = 1024 KB 1024 Mb 1024 MB Notation Example 14 b 1110b h 0Eh Intel R ® 82845 MCH for SDR Datasheet ...
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... R 1.2 Reference Documents ® Intel Pentium 4 Processor in a 478 Pin Package and Intel SDR Design Guide ® Intel 82801BA I/O Controller Hub (ICH2) and Intel (ICH2-M) Datasheet ® Intel 845 Chipset Thermal and Mechanical Design Guidelines for SDR ® Intel 82802AB/AC Firmware Hub (FWH) Datasheet PCI Local Bus Specification, Revision 2 ...
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... AGTL+ system bus with integrated termination supporting 32-bit system bus addressing (w/ 512 Mb technology) of PC133 SDRAM 1.5 V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability 8 bit, 66 MHz 4x hub interface to the ICH2 Distributed arbitration for highly concurrent operation devices; ICH2 has both bus ® Intel 82845 MCH for SDR Datasheet R ...
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... AGP address translation table, regardless of the originating interface. 1.4.2 System Bus Error Checking The MCH does not generate parity, nor check parity for data, address/request, and response signals on the processor bus. ® Intel 82845 MCH for SDR Datasheet Introduction 15 ...
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... TLB. Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked from a dedicated 66 MHz clock (66IN). The AGP-to-host/core interface is asynchronous. 16 SDR (PC133) Maximum 384 MB 768 MB 1 ® Intel 82845 MCH for SDR Datasheet R ...
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... The AGP and hub interface runs at a constant 66 MHz base frequency. The hub interface runs at 4x. AGP transfers can be 1x, 2x, or 4x. Table 5 indicates the supported frequency ratios between the various interfaces. ® Table 5. Intel MCH Clock Ratio Table Interface Memory ...
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... Introduction 1.4.7 System Interrupts The MCH supports both Intel 8259 and Pentium 4 processor interrupt delivery mechanisms. The serial APIC interrupt mechanism is not supported. Intel 8259 support consists of flushing inbound hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the hub interface. ...
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... MCH. All processor control signals follow normal convention. A “0” indicates an active level (low voltage) if the signal is followed by “#” symbol, and a “1” indicates an active level (high voltage) if the signal has no “#” suffix. ® Intel 82845 MCH for SDR Datasheet Signal Description 19 ...
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... Signal Description ® Figure 1. Intel MCH Simplified Block Diagram HA[31:3]# HD[63:0]# HREQ[4:0]# CPURS T# HADSTB[1:0]# HDS TB P[3:0]/HDSTBN[3:0] SCS[11:0]# SM A[12:0] SDQ[63:0] SCKE[5:0] HI_S TB , HI_STB# 20 ADS# BNR# BP RI# DBSY DRDY# P rocessor AGP HIT# System Interface HITM HLOCK# Interface HTRDY# RS[2:0]# BR0# DBI[3:0]# System ...
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... CPURST# DBSY# DEFER# DBI[3:0]# DRDY# HA[31:3]# HADSTB[1:0]# ® Intel 82845 MCH for SDR Datasheet Type I/O Address Strobe: The system bus owner asserts ADS# to indicate the first AGTL+ of two cycles of a request phase. I/O Block Next Request: BNR# is used to block the current request bus AGTL+ owner from issuing a new request ...
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... Deferred response 011 Reserved (not driven by MCH) 100 Hard Failure (not driven by MCH) 101 No data response 110 Implicit Write back 111 Normal data response Description Data Bits HD[63:48]#, DBI3# HD[47:32]#, DBI2# HD[31:16]#, DBI1# HD[15:0]#, DBI0# ® Intel 82845 MCH for SDR Datasheet R ...
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... Hub Interface Signals Signal Name HI_[10:0] HI_STB HI_STB# ® Intel 82845 MCH for SDR Datasheet Type O Chip Select: These signals select the particular SDRAM components CMOS during the active state. Note: There are two SCS# signals per SDRAM row. These signals can be toggled on every rising system memory clock edge ...
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... SBA bus and the AD bus simultaneously. During PIPE# Operation: Not Used. During FRAME# Operation: Not Used. Note: When sideband addressing is disabled, these signals are isolated (no external/internal pull-up resistors are required). Intel Description ® 82845 MCH for SDR Datasheet R ...
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... RBF# WBF# 2.4.3 AGP Status Signals Signal Name ST[2:0] ® Intel 82845 MCH for SDR Datasheet Type I Read Buffer Full: RBF# indicates if the master is ready to accept AGP previously requested low priority read data. When RBF# is asserted, the MCH is not allowed to initiate the return low priority read data. That is, the MCH can finish returning the data for the request currently being serviced ...
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... STOP: G_STOP Is an input when the MCH acts as a FRAME#-based s/t/s AGP initiator and an output when the MCH acts as a FRAME#-based AGP AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface. Description Description ® Intel 82845 MCH for SDR Datasheet R ...
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... NOTE: PCIRST# from the ICH2 is connected to RSTIN# and is used to reset AGP interface logic within the MCH. The AGP agent will also use PCIRST# provided by the ICH2 as an input to reset its internal logic. ® Intel 82845 MCH for SDR Datasheet Type I/O ...
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... PCI Rev 2.0 and 2.1 specifications. Note: This input needs to be 3.3 V tolerant. I Test Input: This pin is used for manufacturing and board level test CMOS purposes. Note: This signal has an internal pull-up resistor. Description ® Intel 82845 MCH for SDR Datasheet R ...
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... VCC1_8 VCCSM VCCA[1:0] VTT VSS VSSA[1:0] ® Intel 82845 MCH for SDR Datasheet Type Ref Host Reference Voltage: Reference voltage input for the data, address, and common clock signals of the host AGTL+ interface. Ref SDRAM Reference Voltage: Reference voltage input for DQ, DQS, RDCLKIN (SDR) ...
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... Signal Name RSTIN# Assertion AD_STB[1:0] Z AD_STB[1:0]# Z SB_STB I SB_STB# I G_AD[31:0] Z G_C/BE[3:0]# Z G_FRAME# Z/I G_IRDY# Z/I G_TRDY# Z/I G_STOP# Z/I G_DEVSEL# Z/I G_PAR Z AGPREF Z Hub Interface HI_[10:0] Z/I HI_STB Z/I HI_STB# Z/I Clocks BCLK I Miscellaneous RSTIN# I TESTIN# I ® Intel 82845 MCH for SDR Datasheet R ...
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... Note that software does not need to perform a read-merge-write operation for the Configuration Address (CONF_ADDR) register. ® Intel 82845 MCH for SDR Datasheet Register Description Description ...
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... AGP/PCI configuration registers (including the AGP I/O and memory address mapping). Table 6 shows the Device # assignment for the various internal MCH devices. ® Table 6. Intel MCH Internal Device Assignments MCH Function DRAM Controller/8 bit HI_A Controller Host-to-AGP Bridge (virtual P2P) NOTE: A physical PCI bus 0 does not exist ...
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... Configuration cycles to any of the MCH’s internal devices are confined to the MCH and not sent over the hub interface. Accesses to disabled MCH internal devices are forwarded over the hub interface as Type 0 Configuration Cycles. ® Intel 82845 MCH for SDR Datasheet Register Description 33 ...
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... Configuration Address register and the hub interface, onto the PCI bus as an I/O cycle. The CONF_ADDR register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. 34 0CF8h Accessed as a DWord 00000000h R/W 32 bits ® Intel 82845 MCH for SDR Datasheet R ...
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... Register Number. This field selects one register within a particular bus, device, and function as specified by the other fields in the Configuration Address register. This field is mapped to GAD[7:2] during AGP configuration cycles and A[7:2] during hub interface configuration cycles. 1:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description Descriptions 35 ...
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... Table 7. Memory-mapped Register Address Map Memory Address Offset 020h–02Bh 2Ch 02Dh–02Fh 030h–034h 040h–0DFh 140h–1DFh 36 0CFCh 00000000h R/W 32 bits Descriptions Register Group Reserved DRAM Width Register Reserved Strength Registers Reserved Reserved ® Intel 82845 MCH for SDR Datasheet R ...
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... Note: Since there are multiple clock signals assigned to each row of a DIMM important to clarify exactly which row width field affects which clock signal. Row Parameters ® Intel 82845 MCH for SDR Datasheet 2Ch 00h R/W 8 bits Descriptions SDR Clocks Affected SCK[0], SCK[2] SCK[1], SCK[3] ...
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... X 3 Reserved. 2:0 SDQ/SDQS Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4. 30h 00h R/W 8 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... SCKE x8 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X ® Intel 82845 MCH for SDR Datasheet Register Description 31h 00h R/W 8 bits Descriptions 39 ...
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... X 3 Reserved. 2:0 SCS# x8 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4. 32h 00h R/W 8 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... CK x8 Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X ® Intel 82845 MCH for SDR Datasheet Register Description 33h 00h R/W 8 bits Descriptions 41 ...
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... Receive Enable Out Signal Group (RCVEnOut) Strength Control. This field selects the signal drive strength. 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4. 34h 00h R/W 8 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... Host-Hub Interface Bridge Device Registers (Device 0) Table 8 provides the register address map for Device 0 PCI configuration space. An “s” in the Default Value column indicates that a strap determines the power-up default value for that bit. ® Table 8. Intel MCH Configuration Space (Device 0) Address Register Offset Symbol 00– ...
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... AGP Low Priority Transaction Timer Reserved Top of Low Memory MCH Configuration Error Status Error Command SMI Command SCI Command Reserved. Scratchpad Data Reserved. Product Specific Capability Identifier Reserved. ® Intel R Default Access Value — — 00000000h RO 0000000000 RO, R/W 0000h 00h R/W — ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the DID Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.5.2 DID—Device Identification Register (Device 0) ...
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... Bus Master Enable (BME)—RO. Hardwired to 1. The MCH is always enabled as a master on the hub interface. 1 Memory Access Enable (MAE)—RO. Not implemented; Hardwired to 1. The MCH always allows access to system memory. 0 I/O Access Enable (IOAE)—RO. Not implemented; Hardwired 04–05h 0006h R/ bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... A list of new capabilities is accessed via the CAPPTR Register (offset 34h). CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides. 3:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description 06–07h 0090h RO, R/WC ...
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... Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the MCH. 06h = Bridge device. 48 08h See table below RO 8 bits Description 0Ah 00h RO 8 bits Description 0Bh 06h RO 8 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... HDR—Header Type Register (Device 0) Address Offset: Default: Access: Size: This register identifies the header layout of the configuration space. Bit 7:0 Hardwired to 00h. Writes have no effect. ® Intel 82845 MCH for SDR Datasheet Register Description 0Dh 00h RO 8 bits Description 0Eh 00h ...
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... Type—RO. These bits determine addressing type and they are hardwired to “00” to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space. 0 Memory Space Indicator—RO. Hardwired identify aperture range as a memory range. 50 10–13h 0000_0008h R/ bits Description ® Intel 82845 MCH for SDR Datasheet R register ...
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... Bit 7:0 AGP Standard Register Block Pointer Address. This address pointer indicates to software where it can find the beginning of the AGP register block. E4h = AGP register block beginning address. ® Intel 82845 MCH for SDR Datasheet Register Description 2C–2Dh 0000h R/WO 16 bits Description 2E– ...
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... DRAM Row Boundary Address. This 8 bit value defines the upper and lower addresses for each DRAM row. This 8-bit value is compared against a set of address lines to determine the upper address limit of a particular row. 52 51h 00h R/W 8 bits Descriptions 60–67h (DRB0–DRB7) 00h R/W 8 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... Row 73h (RAODD and RAEVEN fields must contain default value of 00h Rsvd 7 6 Rsvd 7 6 Rsvd 7 6 Rsvd ® Intel 82845 MCH for SDR Datasheet 70–73h (DRA0–DRA3) 00h R/W 8 bits 4 3 Row attribute for Row 1 Rsvd 4 3 Row attribute for Row 3 Rsvd ...
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... KB 100 = 16 KB Others = Reserved 3 Reserved. 2:0 Row Attribute for Even-Numbered Row (RAEVEN). This 3-bit field defines the page size of the corresponding row. 001 = 2 KB 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Reserved 54 Description ® Intel 82845 MCH for SDR Datasheet R ...
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... Reserved. 0 DRAM RAS# Precharge (tRP). This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row DRAM clocks DRAM clocks ® Intel 82845 MCH for SDR Datasheet Register Description 78–7Bh 00000010h R/W 32 bits ...
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... Refresh enabled. Refresh interval 15.6 us 010 = Refresh enabled. Refresh interval 7.8 us 011 = Refresh enabled. Refresh interval 64 us 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved 7 Reserved. 56 7C–7Fh 00000000h R/ bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... CBR Refresh Enable. In this mode all processor cycles to system memory result in a CBR cycle on the SDRAM interface 111 = Normal operation. 3:2 Reserved. 1:0 DRAM Type (DT)—RO. Used to select between supported SDRAM types Single Data Rate (SDR) SDRAM. 01–11 = Reserved ® Intel 82845 MCH for SDR Datasheet Register Description Description 57 ...
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... Reserved. 58 86h 00h RO 8 bits Description 8C–8Fh 0000_0000h RO 32 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... Bits [7, 3] Bits [6, 2] Reserved Reserved ® Intel 82845 MCH for SDR Datasheet 90–96h (PAM0–PAM6) 00h R/ bits Bits [5, 1] Bits [ Disabled. System memory is disabled and all accesses are directed to the hub interface. The MCH does not respond as a PCI target for any read or write access to this area ...
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... PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 Reserved Read Enable (R/W) 1=Enable Reserved 0=Disable Offset 96h 95h 94h 93h 92h 91h 90h Read Enable (R/W) 1=Enable 0=Disable Write Enable (R/W) 1=Enable 0=Disable Reserved pam ® Intel 82845 MCH for SDR Datasheet R ...
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... AGP. Expansion Area (C0000h–DFFFFh) This 128 KB area is divided into eight 16 KB segments, which can be assigned with different attributes via PAM control register as defined by the table above. ® Intel 82845 MCH for SDR Datasheet Attribute Bits Memory Segment Reserved ...
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... ICH2 through the hub interface. The hub interface cycles matching an enabled hole will be ignored by the MCH. Note that a selected hole is not re- mapped Disabled. No hole MB– hole) 6:0 Reserved. 62 97h 00h R/W 8 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... SMM space. “SMM DRAM” is not remapped simply “made visible” if the conditions are right to access SMM space, otherwise the access is forwarded to the hub interface. 010 = Hardwired to 010 to indicate that the MCH supports the SMM space at A0000h–BFFFFh. ® Intel 82845 MCH for SDR Datasheet Register Description 9Dh 02h ...
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... MB of additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes read only. 64 9Eh 38h RO, R/W, R/WC, R/W/L 8 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... AGP Capability ID (CAPID). This field identifies the linked list item as containing AGP registers. This field has a value of 0000_0010b assigned by the PCI SIG. ® Intel 82845 MCH for SDR Datasheet Register Description A0–A3h 0020_0002h RO ...
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... MCH Note: The selected data transfer mode applies to both AD bus and SBA bus. It also applies to Fast Writes if they are enabled. 66 A4–A7h 1F00_0217h RO 32 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... AGP master (after that capability has been verified by accessing the same functional register in the AGP masters’ configuration space.) Note: This field applies to AD and SBA buses. It also applies to Fast Writes if they are enabled. ® Intel 82845 MCH for SDR Datasheet Register Description A8–ABh ...
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... The RATE[2:0] bit in the AGPSTS register will be read as a 001. This bit allows the BIOS to force 1x mode. Note that this bit must be set by the BIOS before AGP configuration. 68 B0–B3h 0000_0000h R/W 32 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond as “hardwired” to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling APBASE[27:25] as read/write. ® Intel 82845 MCH for SDR Datasheet B4h 00h R/W ...
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... Aperture Translation Table Base (TTABLE). This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in system memory. Note: It should be modified only when the GTLB has been disabled. 11:0 Reserved. 70 B8–BBh 0000_0000h R/W 32 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... MHz clock granularity) allotted to the current agent (either AGP master or MCH) after which the AGP arbiter will grant the bus to another agent. 2:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description BCh 00h R/W ...
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... Low Priority Transaction Timer Count Value (LPTTC). The number of clocks programmed in these bits represents the guaranteed time slice (measured in eight 66 MHz clock granularity) allotted to the current low priority AGP transaction data transfer state. 2:0 Reserved. 72 BDh 00h R/W 8 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... Programming Example: 400h = 1 GB. An access to 4000_0000h or above will be considered above the TOM and therefore not routed to system memory. It may go to AGP, aperture, or subtractively decode to the hub interface. 3:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description C4–C5h 0100h R/W ...
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... The MCH forwards accesses to the IOAPIC regions to the appropriate interface, as specified by the memory and PCI configuration registers. 0 Reserved. 74 C6–C7h 0000h R/ bits Description 0B0000h–0B7FFFh 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode) Intel R ® 82845 MCH for SDR Datasheet ...
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... A memory read data transfer had an uncorrectable multiple-bit error. When this bit is set, the address and device number that caused the error are logged in the EAP Register. Software uses bits [1:0] to detect whether the logged error address is for Single or Multiple-bit error. ® Intel 82845 MCH for SDR Datasheet Register Description C8–C9h ...
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... Device 0 is globally enabled in the PCICMD register Disable. MCH does not generate an SERR message for this event Enable. MCH generates a SERR message over the hub interface when an unimplemented Special Cycle is received on the hub interface. 76 Description CA–CBh 0000h R/W 16 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... SERR on Single-bit ECC Error (DSERR Disable. For systems that do not support ECC, this bit must be disabled Enable. Generation of the hub interface SERR message is enabled when the MCH system memory controller detects a single bit error. ® Intel 82845 MCH for SDR Datasheet Register Description Description 77 ...
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... CC–CDh 0000h R/W 16 bits that when an SMI error message is enabled for an error condition, sure Description CE–CDh 0000h R/W 16 bits sure that when an SCI error message is enabled for an error condition, SERR Description Intel R ® 82845 MCH for SDR Datasheet ...
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... Next Capability Pointer. A0h = Points to the next Capability ID in this device (ACAPID register). (default) 7:0 CAP_ID. 1001b = Identifies the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. (default) ® Intel 82845 MCH for SDR Datasheet Register Description DE–DFh 0000h R/W 16 bits ...
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... Bridge Registers (Device 1) Table 10. provides the register address map for Device 0 PCI configuration space. An “s” in the Default Value column indicates that a strap determines the power-up default value for that bit. ® Table 10. Intel MCH Configuration Space (Device 1) Address Symbol Offset ...
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... The VID1 register contains the vendor identification number. This 16-bit register combined with the DID1 Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.6.2 DID1—Device Identification Register (Device 1) Address Offset: ...
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... I/O Access Enable (IOAE1)—R/ Disable. All of device 1’s I/O space is disabled Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, and IOLIMIT1 registers. 82 04–05h 0000h RO, R/W 16 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... Fast Back-to-Back (FB2B1)—RO. Hardwired to 1. The AGP port always supports fast back to back transactions. 6 Reserved MHz Capability (CAP66)—RO. Hardwired to 1. Indicates that the AGP port is 66 MHz capable. 4:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description 06–07h 00A0h RO, R/WC 16 bits Descriptions 83 ...
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... Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the MCH device 1. 06h = Bridge device. 84 08h See RID1 table below RO 8 bits Description 0Ah 04h RO 8 bits Description 0Bh 06h RO 8 bits Description ® Intel 82845 MCH for SDR Datasheet R ...
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... PBUSN1—Primary Bus Number Register (Device 1) Offset: Default: Access: Size: This register identifies that “virtual” PCI-PCI Bridge is connected to bus #0. Bit 7:0 Bus Number. Hardwired to 0. ® Intel 82845 MCH for SDR Datasheet Register Description 0Dh 00h R/W 8 bits Description 0Eh 01h ...
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... This register identifies the subordinate bus (if any) that resides at the level below AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP. Bit 7:0 Bus Number. Programmable. Default = 0. 86 19h 00h R/W 8 bits Descriptions 1Ah 00h R/W 8 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
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... When the MLT is disabled, the burst time for the MCH is unlimited (i.e., the MCH can burst forever). Bit 7:3 Secondary MLT Counter Value. Default=0s (i.e., SMLT disabled) 2:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description 1Bh 00h R/W 8 bits Description ...
Page 88
... FFFh. Thus, the top of the defined I/O address range is at the top aligned address block. Bit 7:4 I/O Address Limit. Corresponds to A[15:12] of the I/O address. (Default=0) 3:0 Reserved. (Only 16-bit addressing supported.) 88 1Ch F0h R/W 8 bits O_LIMIT Description 1Dh 00h R/W 8 bits IO_LIMIT Description ® Intel R 82845 MCH for SDR Datasheet ...
Page 89
... Fast Back-to-Back (FB2B1)—RO. Hardwired to 1. MCH as a target supports fast back-to-back transactions on AGP. 6 Reserved MHz Capable (CAP66)—RO. Hardwired to 1. AGP bus is capable of 66 MHz operation. 4:0 Reserved. ® Intel 82845 MCH for SDR Datasheet Register Description 1E–1Fh 02A0h RO, R/WC 16 bits Descriptions 89 ...
Page 90
... USWC space attributes to be performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP memory access performance. 90 20–21h FFF0h R/W 16 bits address MEMORY_LIMIT1 Description 22–23h 0000h R/W 16 bits address MEMORY_LIMIT1 Description Intel R ® 82845 MCH for SDR Datasheet ...
Page 91
... Note: Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) from the processor perspective. ® Intel 82845 MCH for SDR Datasheet Register Description 24–25h ...
Page 92
... KB block, even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead of going to AGP, these cycles are forwarded to PCI0 where they can be subtractively or positively claimed by the ISA bridge. Reserved 3Eh 00h RO, R/W 8 bits Descriptions ® Intel 82845 MCH for SDR Datasheet R ...
Page 93
... MCH does not assert an SERR message upon receipt of a target abort on AGP. SERR messaging for Device 1 is globally enabled in the PCICMD1 register MCH generates an SERR message over the hub interface when a target abort is received on AGP. ® Intel 82845 MCH for SDR Datasheet Register Description Descriptions 40h ...
Page 94
... Write thermal management begins based on the settings in WTMW and WTHM, and remains in effect until this bit is reset Reserved. 94 50–57h 00h R/W/L 64 bits Descriptions host clocks (@ 100 MHz) seconds once invoked (128 * 4* host clocks * 16). ® Intel 82845 MCH for SDR Datasheet R to ...
Page 95
... Read thermal management stops and the counters associated with RTMW and RTHM are reset Read thermal management begins based on the settings in RTMW and RTHM, and remains effect until this bit is reset to 0. ® Intel 82845 MCH for SDR Datasheet Register Description 58–5Fh 0000_0000_0000_0000h ...
Page 96
... Register Description 96 This page is intentionally left blank. Intel R ® 82845 MCH for SDR Datasheet ...
Page 97
... PCI configuration portion of the BIOS software will program the TOM register to the maximum value that is less than the amount of memory in the system and that allows enough room for all populated PCI devices. ® Intel 82845 MCH for SDR Datasheet 16 GB Range ...
Page 98
... FEC8_0000 FEC0_0000 Low Mem ory (TOM TSEG 100C_0000 100A_0000 0100_0000 (16 MB) = System Mem ory Region 00F0_0000 (15 MB) = Optional System Mem ory Region 0010_0000 (1 MB) ® Intel R Controlled by PAM[6:0] Controlled by VGA Enable and MDA Enable sys_addr_map_2 sys_addr_map_3 82845 MCH for SDR Datasheet ...
Page 99
... SMM-encoded request for code (not data), then the transaction is steered to system memory rather than the hub interface. Under these conditions, the VGA_EN1 bit and the MDAP bit are ignored. ® Intel 82845 MCH for SDR Datasheet System Address Map 99 ...
Page 100
... BIOS software may optionally open a “window” between 15 MB and 16 MB (0_00F0_0000h to 0_00FF_FFFFh) that relays transactions to the hub interface instead of completing them with a system memory access. This window is opened by programming the FDHC.HEN configuration field. 100 ® Intel 82845 MCH for SDR Datasheet R ...
Page 101
... ESMRAMC.H_SMRAME allows access to high SMRAM space. SMM memory accesses from any hub interface or AGP are specially terminated: reads are provided with the value from address 0 while writes are ignored entirely. ® Intel 82845 MCH for SDR Datasheet System Address Map 101 ...
Page 102
... AGP device. Note: The MCH device 1 memory range registers described above are used to allocate memory address space for any devices sitting on AGP bus that require such a window. 102 Address Memory_Limit_Address Address Prefetchable_Memory_Limit_Address ® Intel 82845 MCH for SDR Datasheet R ...
Page 103
... The above 1 MB solutions require changes to compatible SMRAM handlers’ code to properly execute above 1 MB. Note: Masters from the hub interface and AGP are not allowed to access the SMM space. ® Intel 82845 MCH for SDR Datasheet System Address Map 103 ...
Page 104
... Any address translated through the AGP Aperture GTLB must not target system memory from 000A0000h to 000FFFFFh. 104 Transaction Address Space A0000h to BFFFFh A0000h to BFFFFh 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh (TOM–TSEG_SZ) to TOM (TOM–TSEG_SZ) to TOM ® Intel 82845 MCH for SDR Datasheet R System Memory Space ...
Page 105
... Memory writes to VGA range on AGP if enabled. All memory reads from the hub interface that target >4 GB memory range are terminated with a master abort completion, and all memory writes (>4 GB) from the hub interface are ignored. ® Intel 82845 MCH for SDR Datasheet System Address Map 105 ...
Page 106
... AGP PIPE# and SBA accesses are limited to 256 bytes and must hit system memory. Read accesses crossing a device boundary will return invalid data when the access crosses out of system memory. Write accesses crossing out of system memory will be discarded. The IAAF Error bit will be set. 106 ® Intel 82845 MCH for SDR Datasheet R ...
Page 107
... DBI# signal will be asserted and the data will be inverted prior to being driven on the bus. When the processor or the MCH receives data, it monitors DBI[3:0]# to determine if the corresponding data segment should be inverted. ® Intel 82845 MCH for SDR Datasheet Data Bits HD[15:0]# HD[31:16]# ...
Page 108
... Once posted, the memory write from AGP or the hub interface to address 0FEEx_xxxxh is decoded as a cycle that needs to be propagated by the MCH to the system bus as an Interrupt Message Transaction. 108 ® Intel 82845 MCH for SDR Datasheet R ...
Page 109
... DIMM is equivalent to a “row” of SDRAM devices. Table 12. Supported DIMM Configurations Density 64 Mbit Device X8 Width Single \ SS/DS Double 168 pin SDR 128 MB DIMMs ® Intel 82845 MCH for SDR Datasheet 128 Mbit X16 X8 X16 X8 SS/DS SS/DS SS/DS SS/ 128 256 ...
Page 110
... MCH memory interface. SMBus Configuration and Access of the Serial Presence Detect Ports For more details on SMBus Configuration and Serial Present Detect Ports, see the Intel I/O Controller Hub 2 (ICH2) and 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) Datasheet. Memory Register Programming This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs ...
Page 111
... KB 512 Mb 8Meg 4bks 256 MB 13x10x2 Row 8 KB 512 Mb 16Meg 4bks 512 MB 13x11x2 Row 16 KB ® Intel 82845 MCH for SDR Datasheet to the SDRAM memory array is provided by the SBS[1:0] and SMA[12:0] Row Addr BA1 BA0 A12 A11 A10 Col Row 24 11 ...
Page 112
... As an initiator, the MCH does not initiate cycles using AGP enhanced protocols. The MCH supports AGP cycles targeting the interface to system memory only. The MCH supports interleaved AGP PIPE# and AGP FRAME#, or AGP SBA[7:0] and AGP FRAME# transactions. 112 ® Intel 82845 MCH for SDR Datasheet R ...
Page 113
... R Table 15. AGP Commands Supported by the Intel AGP Command Read Hi-Priority Read Reserved Reserved Write Hi-Priority Write Reserved Reserved Long Read Hi-Priority Long Read Flush Reserved Fence Reserved Reserved Reserved NOTES: 1. N/A refers to a function that is not applicable As a target of an AGP cycle, the MCH supports all the transactions targeting system memory (summarized in Table 15) ...
Page 114
... AGPCMD.DRATE field is 1, the data transfers occur using 2x strobing. If bit 0 of AGPCMD.DRATE field is 1, Fast Writes are disabled and data transfers occur using standard PCI protocol. Note that only one of the three DRATE bits can be set by initialization software (Table 16). 114 ® Intel 82845 MCH for SDR Datasheet R ...
Page 115
... LOCK#, SERR#, and PERR# signals are not supported. MCH Initiator and Target Operations Table 17 summarizes MCH target operation for AGP FRAME# initiators. The cycles can be either destined to system memory or the hub interface. Table 17. PCI Commands Supported by the Intel PCI Command Interrupt Acknowledge Special cycle I/O Read ...
Page 116
... C/BE[3:0]# Encoding Cycle Destination 1101 N/A 1110 System Memory 1110 Hub interface 1111 System memory 1111 Hub interface ® Intel 82845 MCH for SDR Datasheet R ® Intel MCH Response as a FRAME# Target No response Read No response Posts data Posts Data ...
Page 117
... Stop-Grant State: This function can be enabled or disabled via a configuration bit. When this function is enabled, STPCLK# is asserted to place the processor into the C2 state with a programmable duty cycle. This is an ACPI defined function but BIOS or APM (via BIOS) can use this facility. ® Intel 82845 MCH for SDR Datasheet Functional Description 117 ...
Page 118
... Pentium 4 Processor in a 478 Pin Package and Intel Design Guide. ® 5.6 Intel MCH System Reset and Power Sequencing For details on MCH system reset and power sequencing, refer to the Intel a 478 Pin Package and Intel 118 ® 845 Chipset Platform Design Guide. ® ...
Page 119
... V system memory supply current VCCSM I 3.3 V standby supply current SUS_3.3 HVREF, AGPREF, HI_REF, SDREF supply current NOTES: 1. These current levels can happen simultaneously, and can be summed into one supply. ® Intel 82845 MCH for SDR Datasheet Parameter Min -55 -0.72 -0.88 -2.83 -0.55 Parameter ...
Page 120
... G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0], G_C/BE[3:0]#, G_PAR PIPE#, SBA[7:0], RBF#, WBF#, SB_STB, SB_STB#, G_REQ# ST[2:0], G_GNT# AGPREF HI_[10:0], HI_STB, HI_STB# HI_REF SDQ[63:0], SCB[7:0] SCS[11:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#, SCKE[5:0], SCK[11:0], RDCLKO RDCLKI SDREF TESTIN# RSTIN# (3.3V) VTT ® Intel 82845 MCH for SDR Datasheet R ...
Page 121
... Signal Signal Type Group (s) 1.5 V Core and AGP Voltage (t) 1.8 V Hub Interface Voltage (u) 3.3 V PC133 SDRAM I/O Voltage (v) CMOS Clock Input (w) CMOS Clock Input ® Intel 82845 MCH for SDR Datasheet Signals VCC1_5 VCC1_8 VCCSM 66IN BCLK, BCLK# Electrical Characteristics 121 ...
Page 122
... VCCSM 0.48 x VCC1_5 1/2 x VCC1_5 0.52 x VCC1_5 (2/3 x VTT) – 0.1 (2/3 x VTT) + 0.1 (1/3 x VTT) + 0.1 VTT-0.1 VTT / 0.75Rtt max ±15 1.0 SDREF – 2.0 SDREF + 2.0 0.4 2 100 ® Intel 82845 MCH for SDR Datasheet R Unit Notes Rtt = 45 ...
Page 123
... Input Capacitance IN RSTIN# Signals V (p) Input Low Voltage IL V (p) Input High Voltage IH I (p) Input Leakage Current LEAK ® Intel 82845 MCH for SDR Datasheet Min Typ Max 4.65 5.37 0.4 x VCC1_5 0.6 x VCC1_5 0.15 x VCC1_5 0.85 x VCC1_5 1 -0.2 15 1.32 1.92 HI_REF – 0.15 HI_REF + 0 ...
Page 124
... Electrical Characteristics 124 This page is intentionally left blank. Intel R ® 82845 MCH for SDR Datasheet ...
Page 125
... MCH ballout listed alphabetically by signal name. The following notes apply to the ballout. Note Connect. Note: RSVD = These pins should not be connected and should be allowed to float. Note: VSS = Connect to ground. ® Intel 82845 MCH for SDR Datasheet Ballout and Package Information 125 ...
Page 126
... Ballout and Package Information ® Figure 6. Intel 82845 MCH Ballout Diagram (Top View—Left Side VSS VCC1_5 AH SBA0 SBA1 G_GNT# AG VCC1_5 SBA2 SBA3 ST2 AF SB_STB SB_STB# AE VSS SBA4 SBA5 VCC1_5 GRCOMP AC VCC1_5 AD_STB1# AD_STB1 VSS G_AD28 AB G_AD20 G_AD22 G_AD19 AA VSS G_AD18 ...
Page 127
... R ® Figure 7. Intel 82845 MCH Ballout Diagram (Top View—Right Side VSS VSS HD49# HD44# HD52# HD48# HD45# HD42# HD43# HD51# VSS HD47# VSS HD41# HD53# HD46# HD40# HDSTBN2# HD36# VSS HSWNG1 VSS HDSTBP2# VSS HD50# HRCOMP1 HD33# HD32# HD39# VSS ...
Page 128
... Ballout and Package Information ® Table 22. Intel 82845 MCH Ballout Listed Alphabetically by Signal Name Signal Name 66IN P22 AD_STB0 R24 AD_STB0# R23 AD_STB1 AC27 AD_STB1# AC28 ADS# V3 AGPREF AA21 BCLK# K8 BCLK J8 BNR# W3 BPRI# Y7 BR0# V7 CPURST# AE17 DBSY# V5 DEFER# Y4 DBI0# AD5 DBI1# ...
Page 129
... AA2 HD1# AB5 HD2# AA5 HD3# AB3 HD4# AB4 HD5# AC5 HD6# AA3 HD7# AA6 ® Intel 82845 MCH for SDR Datasheet Ballout and Package Information Ball # Signal Name HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# ...
Page 130
... HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HSWNG0 HSWNG1 HTRDY# HVREF NC PIPE# RBF# RDCLKIN RDCLKO RS0# RS1# RS2# RSTIN# RSVD SBA0 SBA1 SBA2 SBA3 ® Intel 82845 MCH for SDR Datasheet R Ball # M27 N28 M24 P26 N25 N24 P27 AC2 AC13 AA7 AD13 U7 ...
Page 131
... H23 SCS1# J23 SCS2# G7 SCS3# G8 SCS4# J24 SCS5# G24 SCS6# H7 SCS7# F7 SCS8# G25 ® Intel 82845 MCH for SDR Datasheet Ballout and Package Information Ball # Signal Name SCS9# SCS10# SCS11# SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 ...
Page 132
... SMA8 SMA9 SMA10 SMA11 SMA12 SMRCOMP SRAS# ST0 ST1 ST2 SWE# TESTIN# VCC1_5 VCC1_5 VCCA1 VCCA0 VCC1_8 VCCSM ® Intel 82845 MCH for SDR Datasheet R Ball # D16 B15 C14 J9, J21 G22 E21 F21 G21 E20 G20 E19 F19 G19 G18 E17 ...
Page 133
... AE29, AF5, AF7, AF9, AF11, AF13, AF15, AF17, AF19, AF21, AF25, AG1, AG18, AG20, AG22, AH19, AH21, AH23, AJ3, AJ5, AJ7, AJ9, AJ11, AJ13, AJ15, AJ17, AJ27 ® Intel 82845 MCH for SDR Datasheet Ballout and Package Information Ball # Signal Name VSSA1 VSSA0 ...
Page 134
... Ballout and Package Information 7.1 Package Mechanical Information This section provides the MCH package mechanical dimensions. The package is a 593 ball FC-BGA. ® Figure 8. Intel MCH FC-BGA Package Dimensions (Top and Side View) 16.95 33.90 0.600 ±0.100 Units = M illim eters 134 Top View 37 ...
Page 135
... R ® Figure 9. Intel MCH FC-BGA Package Dimensions (Bottom View) 1.270 Note: All dim ensions are in m illim eters ® Intel 82845 MCH for SDR Datasheet 35.560 17.780 Ballout and Package Information 35.560 17.780 1.270 pkg-MC H_olga_593_Bot 135 ...
Page 136
... Ballout and Package Information 136 This page is intentionally left blank. Intel R ® 82845 MCH for SDR Datasheet ...
Page 137
... XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition of RSTIN#. The signals that need to be pulled are as follows: G_GNT (Global strap enable) SBA1 = 0 (XOR strap) ST2 = 0 (PLL Bypass mode recommended to enter PLL Bypass in XOR test mode) ® Intel 82845 MCH for SDR Datasheet Input Input Testability XOR ...
Page 138
... Input 15 HA9# Input 16 HA11# Input 17 HA5# Input 18 HA16# Input 19 HA12# Input 20 HA10# Input 21 HA8# Input 23 HA14# Input 24 HA15# Input 25 HA28# Input 26 HA18# Input 27 HA20# Input 28 HA19# Input 29 HA26# Input 30 HA22# Input Initial Logic Level ® Intel 82845 MCH for SDR Datasheet R ...
Page 139
... R Chain 0 Ball Element # AH28 ® Intel 82845 MCH for SDR Datasheet Signal Name Note 31 HA24# Input 32 HA23# Input 33 HA17# Input 34 HA25# Input 35 HA21# Input 36 HA27# Input 37 HA30# Input 38 HA31# Input 39 HA29# Input 40 SCS11# Input 41 RDCLKIN Input 42 RDCLKO Input 43 SCK10 Input 44 SCS10# ...
Page 140
... SDQ27 Input 21 SDQ62 Input 22 SDQ60 Input 23 SDQ28 Input 24 SDQ26 Input 25 SDQ58 Input 26 SDQ24 Input 27 RSVD Input 28 SDQ23 Input 29 SDQ57 Input 30 SDQ53 Input 31 SDQ5 Input 32 SDQ20 Input 33 SDQ56 Input 34 SBA1 Output Initial Logic Level N/A ® Intel 82845 MCH for SDR Datasheet R ...
Page 141
... G13 F15 E15 G16 E16 E18 F17 F19 G18 G20 G19 F21 G21 E22 G24 G23 G25 H23 J25 AG28 ® Intel 82845 MCH for SDR Datasheet Signal Name Note 1 SDQ54 Input 2 SDQ21 Input 3 SDQ52 Input 4 SDQ22 Input 5 SDQ19 Input 6 SDQ16 ...
Page 142
... Input 20 SDQ13 Input 21 SDQ45 Input 22 SDQ12 Input 23 SDQ11 Input 24 SMA4 Input 25 SDQ44 Input 26 SMA1 Input 27 SDQ10 Input 28 SDQ42 Input 29 SDQ40 Input 30 RSVD Input 31 SDQ9 Input 32 SDQ7 Input 33 SMA0 Input 34 SDQ41 Input Initial Logic Level ® Intel 82845 MCH for SDR Datasheet R ...
Page 143
... Element # D26 F25 B28 C28 E28 J24 F26 H25 K25 J23 F27 K23 G28 G27 M27 M24 N28 L28 M25 ® Intel 82845 MCH for SDR Datasheet Signal Name Note 35 SDQ6 Input 36 SDQ38 Input 37 SDQ3 Input 38 SDQ35 Input 39 SDQ36 Input 40 RSVD ...
Page 144
... G_AD14 Input 41 G_AD10 Input 42 G_AD15 Input 43 G_AD11 Input 44 SBA4 Output Signal Name Note 1 G_C/BE0# Input 2 G_DEVSEL# Input 3 G_PAR Input 4 G_C/BE2# Input 5 G_IRDY# Input 6 G_C/BE1# Input 7 G_FRAME# Input Initial Logic Level N/A Initial Logic Level ® Intel 82845 MCH for SDR Datasheet R ...
Page 145
... AB25 AB23 AB24 AC24 AC22 AB24 AE22 AF24 AF22 AF27 AH25 AG25 AG24 AG26 AH17 AG16 AG17 AC16 AE11 AE27 ® Intel 82845 MCH for SDR Datasheet Signal Name Note 8 G_TRDY# Input 9 WBF# Input 10 G_STOP# Input 11 G_C/BE3# Input 12 G_AD18 Input 13 G_AD17 ...
Page 146
... Input 20 HD45# Input 21 HD40# Input 22 HD46# Input 23 DBI2# Input 24 HD43# Input 25 HD44# Input 26 HD38# Input 27 HD42# Input 28 HDSTBN2# Input 29 HD41# Input 30 HD36# Input 31 HD33# Input 32 HD32# Input 33 HD39# Input 34 HD34# Input Initial Logic Level ® Intel 82845 MCH for SDR Datasheet R ...
Page 147
... AF8 AE6 AG4 AH3 AE8 AG2 AF4 AH2 AE5 AG3 AF3 AD7 AC7 AC8 AD5 AC6 AE2 AB7 AE3 AD4 ® Intel 82845 MCH for SDR Datasheet Signal Name Note 35 HD35# Input 36 HD37# Input 37 HD24# Input 38 HD31# Input 39 HD27# Input 40 DEFER# ...
Page 148
... HD6# Input 32 HD4# Input 33 HD0# Input 34 HIT# Input 35 BPRI# Input 36 RS2# Input 37 HITM# Input 38 HTRDY# Input 39 HLOCK# Input 40 BR0# Input 41 BNR# Input 41 RS0# Input 43 DBSY# Input 44 DRDY# Input 45 SBA7 Output Initial Logic Level N/A ® Intel 82845 MCH for SDR Datasheet R ...