RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 47

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.5.4
Intel
®
82845 MCH for SDR Datasheet
R
PCISTS—PCI Status Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0s on the
hub interface. Since MCH Device 0 is the Host-to-hub interface bridge, many of the bits are not
implemented.
10:9
Bit
6:5
3:0
15
14
13
12
11
8
7
4
Reserved.
Signaled System Error (SSE)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH Device 0 generated an SERR message over the hub interface for any enabled Device
Received Master Abort Status (RMAS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH generated a hub interface request that receives a Master Abort completion packet or
Received Target Abort Status (RTAS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH generated a hub interface request that receives a Target Abort completion packet or
Signaled Target Abort Status (STAS)—RO. Not Implemented; Hardwired to 0. The MCH will
not generate a Target Abort hub interface completion packet or special cycle.
DEVSEL Timing (DEVT)—RO. Hardwired to 00. Hub interface does not comprehend
DEVSEL# protocol.
Master Data Parity Error Detected (DPD)—RO. Not Implemented; Hardwired to 0. PERR
signaling and messaging are not implemented by the MCH.
Fast Back-to-Back (FB2B)—RO. Hardwired to 1.
Reserved.
Capability List (CLIST)—RO.
1 = Indicates to the configuration software that this device/function implements a list of new
Reserved.
0 error condition. Device 0 error conditions are enabled in the PCICMD and ERRCMD
Registers. Device 0 error flags are read/reset from the PCISTS or ERRSTS Registers.
Master Abort Special Cycle.
Target Abort Special Cycle.
capabilities. A list of new capabilities is accessed via the CAPPTR Register (offset 34h).
CAPPTR contains an offset pointing to the start address within configuration space of this
device where the AGP Capability standard register resides.
06–07h
0090h
RO, R/WC
16 bits
Description
Register Description
47