RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 38

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RG82845 S L5YQ

Manufacturer Part Number
RG82845 S L5YQ
Description
Manufacturer
Intel
Datasheet

Specifications of RG82845 S L5YQ

Lead Free Status / RoHS Status
Not Compliant
Register Description
3.4.2
38
DQCMDSTR—Strength Control Register (SDQ and CMD
Signal Groups)
Memory Address Offset:
Default Value:
Access:
Size:
This register controls the drive strength of the I/O buffers for the DQ/DQS and CMD signal
groups.
6:4
2:0
Bit
7
3
Reserved.
CMD Strength Control (SRAS#, SCAS#, SWE#, SMA[12:0], SBS[1:0]). This field selects the
signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
Reserved.
SDQ/SDQS Strength Control. This field selects the signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
30h
00h
R/W
8 bits
Descriptions
Intel
®
82845 MCH for SDR Datasheet
R

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