RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 9

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Intel
Intel
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82845 MCH for SDR Datasheet
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82845 MCH Features
Intel
Support
System Memory Support
Hub Interface to Intel
Enhanced Mode Scaleable Bus Protocol
2x Address, 4x Data
System Bus interrupt delivery
400 MHz system bus
System Bus Dynamic Bus Inversion (DBI)
32-bit system bus addressing
12 deep In-Order Queue
AGTL+ bus driver technology with
integrated AGTL+ termination resistors
Directly supports one SDR SDRAM
channel, 64 bits wide (72 bits with ECC)
133 MHz Single Data Rate (SDR) SDRAM
devices
64 Mb, 128 Mb, 256 Mb and 512 Mb
technologies for x8 and x16 devices
By using 64 Mb technology, the smallest
memory capacity possible is 32 MB
Configurable optional ECC operation (single
bit Error Correction and multiple bit Error
Detection)
Page sizes of 2 KB, 4 KB, 8 KB and 16 KB
(individually selected for every row)
Thermal management
Maximum of 3 Double-Sided DIMMs (6
rows populated) with unbuffered PC133
(with or without ECC)
Note: Mixed mode, populating ECC and
Non-ECC Memories simultaneously is not
supported.
3 GB Maximum using 512 Mb technology
Supports up to 24 simultaneous open pages
Maximum memory bandwidth of 1.067 GB/s
with PC133
266 MB/s point-to-point hub interface to
ICH2
66 MHz base clock
MSI interrupt messages, power management
state change, SMI, SCI and SERR error
indication
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Pentium
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4 Processor (478 pin package)
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82801BA ICH2
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Accelerated Graphics Port (AGP) Interface
System Interrupt Support
Power Management
Package
Supports a single AGP device (either a
connector or on the motherboard)
Supports AGP 2.0 including 1x, 2x, and 4x
AGP data transfers and 2x/4x Fast Write
protocol
Supports only 1.5 V AGP electrical
characteristics
32 deep AGP request queue
Delayed
System Memory FRAME# semantic reads
System bus interrupt delivery mechanism
Interrupts signaled as upstream memory
writes from AGP/PCI
Supports peer MSI between hub interface
and AGP
Provides redirection for IPI and upstream
interrupts to the system bus
SMRAM space remapping to A0000h
Supports extended SMRAM space above
256 MB, additional TSEG from Top of
Memory
SMRAM accesses from AGP or hub
interface are not supported
PC ’99 suspend to DRAM support
ACPI, Revision 1.0b compliant power
management
APM, Revision 1.2 compliant power
management
NT Hardware Design Guide, Version 1.0
compliant
MCH: 593 pin FC-BGA (37.5 x 37.5 mm)
transaction support for AGP-to-
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