RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 115

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

5.3.6
Intel
Table 16. Data Rate Control Bits
Table 17. PCI Commands Supported by the Intel
®
82845 MCH for SDR Datasheet
R
AGP FRAME# Transactions on AGP
The MCH accepts and generates AGP FRAME# transactions on the AGP bus. The MCH
guarantees that AGP FRAME# accesses to system memory are kept coherent with the processor
caches by generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not
supported.
MCH Initiator and Target Operations
Table 17 summarizes MCH target operation for AGP FRAME# initiators. The cycles can be either
destined to system memory or the hub interface.
Interrupt Acknowledge
Special cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
AGPCNTL
.FWCE
PCI Command
0
1
1
1
AGPCMD.
FWPE
0
1
1
1
AGPCMD.
DRATE
C/BE[3:0]#
[bit 2]
Encoding
X
0
0
1
0000
0001
0010
0011
0100
0101
0110
0110
0111
0111
1000
1001
1010
1011
1100
1100
AGPCMD.
DRATE
®
[bit 1]
MCH (When Acting as a FRAME# Target)
X
0
1
0
Cycle Destination
System memory
System memory
System memory
Hub interface
Hub interface
Hub interface
AGPCMD.
DRATE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
[bit 0]
X
1
0
0
Intel
MCH =>AGP Master Write
®
MCH
Response as a FRAME#
Functional Description
2x strobing
4x strobing
Protocol
No response
No response
No response
No response
No response
No response
No response
No response
No response
No response
No response
No response
No response
Posts data
1x
1x
Target
Read
Read
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