RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 68

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.5.28
68
AGPCTRL—AGP Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
This register provides for additional control of the AGP interface.
31:8
Bit
6:1
7
0
Reserved.
GTLB Enable (GTLBEN). This bit provides enable and flush control of the GTLB.
0 = Disable (Default). GTLB is flushed by clearing the valid bits associated with each entry.
1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer.
Reserved.
Data Rate 4x Override.
1 = The RATE[2:0] bit in the AGPSTS register will be read as a 001. This bit allows the BIOS to
force 1x mode. Note that this bit must be set by the BIOS before AGP configuration.
B0–B3h
0000_0000h
R/W
32 bits
Description
Intel
®
82845 MCH for SDR Datasheet
R