RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 91

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.6.19
3.6.20
Intel
®
82845 MCH for SDR Datasheet
Note: Prefetchable memory range is supported to allow segregation by the configuration software
R
PMBASE1—Prefetchable Memory Base Address Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the host to AGP prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when
read. The configuration software must initialize this register. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range
will be aligned to a 1 MB boundary.
PMLIMIT1—Prefetchable Memory Limit Address Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the host to AGP prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE1
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when
read. The configuration software must initialize this register. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address
range will be at the top of a 1 MB aligned memory block.
between the memory ranges that must be defined as UC and the ones that can be designated as a
USWC (i.e., prefetchable) from the processor perspective.
15:4
15:4
Bit
3:0
Bit
3:0
Prefetchable Memory Address Limit 1(PMEM_LIMIT1). Corresponds to A[31:20] of the
memory address. (Default=00h)
Reserved.
Prefetchable Memory Address Base 1(PMEM_BASE1). Corresponds to A[31:20] of the
memory address.
Reserved.
24–25h
FFF0h
R/W
16 bits
26–27h
0000h
R/W
16 bits
address
address
Description
Description
PREFETCHABLE_MEMORY_LIMIT1
PREFETCHABLE_MEMORY_LIMIT1
Register Description
91