RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 85

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.6.8
3.6.9
3.6.10
Intel
®
82845 MCH for SDR Datasheet
R
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This functionality is not applicable. It is described here since these bits should be implemented as
a read/write to prevent standard PCI-PCI bridge configuration software from getting “confused”.
HDR1—Header Type Register (Device 1)
Offset:
Default:
Access:
Size:
This register identifies the header layout of the configuration space.
PBUSN1—Primary Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
This register identifies that “virtual” PCI-PCI Bridge is connected to bus #0.
Bit
7:3
2:0
Bit
7:0
Bit
7:0
Not applicable but supports read/write operations. (Reads return previously written data.)
Reserved.
This read only field always returns 01h when read. Writes have no effect.
Bus Number. Hardwired to 0.
0Dh
00h
R/W
8 bits
0Eh
01h
RO
8 bits
18h
00h
RO
8 bits
Descriptions
Descriptions
Description
Register Description
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