RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 30

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.7
30
CPURST#
HADSTB[1:0]#
AP[1:0]#
HA[31:4]#
HD[63:0]#
HDSTBP[3:0]#
HDSTBN[3:0]#
DBI[3:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
BREQ0#
HVREF
Signal Name
Reset States During Reset
Z
ISO
S
H
L
D
I
System Bus Interface
Ti-state
Isolate inputs in inactive state
Strap input sampled during assertion or on the de-asserting edge of RSTIN#
Driven high
Driven low
Strong drive (to normal value supplied by core logic if not otherwise stated)
Input active
Assertion
RSTIN#
During
State
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
L
I
HLRCOMP
HSWNG
SCK[11:0]
SCS[11:0]#
SMA[12:0]
SBS[1:0]
SRAS#
SCAS#
SWE#
SDQ[63:0]
SCB[7:0]
SCKE[5:0]
RDCLKO
RDCLKIN
PIPE#
SBA[7:0]
RBF#
WBF#
G_REQ#
ST[2:0]
G_GNT#
Signal Name
SDR System Memory
AGP
Assertion
RSTIN#
During
ISO/S
State
H/S
L/S
I/S
Z/I
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
I
I
I
I
I
Intel
®
82845 MCH for SDR Datasheet
AD_STB[1:0]
AD_STB[1:0]#
SB_STB
SB_STB#
G_AD[31:0]
G_C/BE[3:0]#
G_FRAME#
G_IRDY#
G_TRDY#
G_STOP#
G_DEVSEL#
G_PAR
AGPREF
HI_[10:0]
HI_STB
HI_STB#
BCLK
RSTIN#
TESTIN#
Signal Name
Miscellaneous
Hub Interface
Clocks
Assertion
RSTIN#
During
State
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z/I
Z
Z
Z
Z
Z
Z
I
I
I
I
I
R